msloniewski cace17e162 targets/de10lite: refactor setting up clock domains ... Use PLL to generate clock for both sys clock domain and clock domain for sdram. Additionally set up clock domain for VGA periph.		2019-12-30 23:25:43 +01:00
..
__init__.py	import: allow importing directly from litex_boards.platforms or litex_boards.targets	2019-09-03 15:30:20 +02:00
ac701.py	targets: keep attributes are no longer needed since automatically added when applying constraints to signals.	2019-12-06 16:01:59 +01:00
de1soc.py	targets: keep attributes are no longer needed since automatically added when applying constraints to signals.	2019-12-06 16:01:59 +01:00
de2_115.py	targets: keep attributes are no longer needed since automatically added when applying constraints to signals.	2019-12-06 16:01:59 +01:00
de10lite.py	targets/de10lite: refactor setting up clock domains	2019-12-30 23:25:43 +01:00
ecp5_evn.py	targets: keep attributes are no longer needed since automatically added when applying constraints to signals.	2019-12-06 16:01:59 +01:00