2015-05-02 04:24:56 -04:00
|
|
|
from migen.fhdl.std import *
|
|
|
|
|
2015-05-09 09:48:54 -04:00
|
|
|
from misoclib.tools.wishbone import WishboneStreamingBridge
|
2015-05-02 04:24:56 -04:00
|
|
|
from misoclib.com.uart.phy.serial import UARTPHYSerial
|
|
|
|
|
2015-05-09 09:48:54 -04:00
|
|
|
class UARTWishboneBridge(WishboneStreamingBridge):
|
2015-05-02 04:24:56 -04:00
|
|
|
def __init__(self, pads, clk_freq, baudrate=115200):
|
|
|
|
self.submodules.phy = UARTPHYSerial(pads, clk_freq, baudrate)
|
2015-05-09 09:48:54 -04:00
|
|
|
WishboneStreamingBridge.__init__(self, self.phy, clk_freq)
|