2013-03-21 05:42:31 -04:00
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#include <stdio.h>
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2013-03-23 19:46:23 -04:00
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#include <stdlib.h>
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2013-03-21 05:42:31 -04:00
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#include <irq.h>
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#include <uart.h>
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2013-05-06 03:56:49 -04:00
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#include <console.h>
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2013-04-14 10:33:00 -04:00
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#include <hw/csr.h>
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#include <hw/flags.h>
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2013-03-21 10:32:26 -04:00
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2013-05-09 04:52:43 -04:00
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static int dvisampler0_d0, dvisampler0_d1, dvisampler0_d2;
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2013-03-23 19:46:23 -04:00
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static void print_status(void)
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{
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2013-05-09 04:52:43 -04:00
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printf("dvisampler0 ph: %4d %4d %4d // %d%d%d [%d %d %d] // %d // %dx%d\n", dvisampler0_d0, dvisampler0_d1, dvisampler0_d2,
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2013-04-14 10:33:00 -04:00
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dvisampler0_data0_charsync_char_synced_read(),
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dvisampler0_data1_charsync_char_synced_read(),
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dvisampler0_data2_charsync_char_synced_read(),
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dvisampler0_data0_charsync_ctl_pos_read(),
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dvisampler0_data1_charsync_ctl_pos_read(),
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dvisampler0_data2_charsync_ctl_pos_read(),
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dvisampler0_chansync_channels_synced_read(),
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dvisampler0_resdetection_hres_read(),
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2013-05-05 05:58:43 -04:00
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dvisampler0_resdetection_vres_read());
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2013-03-23 19:46:23 -04:00
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}
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2013-03-21 10:32:26 -04:00
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static void calibrate_delays(void)
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{
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2013-04-14 10:33:00 -04:00
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dvisampler0_data0_cap_dly_ctl_write(DVISAMPLER_DELAY_CAL);
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dvisampler0_data1_cap_dly_ctl_write(DVISAMPLER_DELAY_CAL);
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dvisampler0_data2_cap_dly_ctl_write(DVISAMPLER_DELAY_CAL);
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while(dvisampler0_data0_cap_dly_busy_read()
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|| dvisampler0_data1_cap_dly_busy_read()
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|| dvisampler0_data2_cap_dly_busy_read());
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dvisampler0_data0_cap_dly_ctl_write(DVISAMPLER_DELAY_RST);
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dvisampler0_data1_cap_dly_ctl_write(DVISAMPLER_DELAY_RST);
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dvisampler0_data2_cap_dly_ctl_write(DVISAMPLER_DELAY_RST);
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dvisampler0_data0_cap_phase_reset_write(1);
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dvisampler0_data1_cap_phase_reset_write(1);
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dvisampler0_data2_cap_phase_reset_write(1);
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2013-05-09 04:52:43 -04:00
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dvisampler0_d0 = dvisampler0_d1 = dvisampler0_d2 = 0;
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2013-03-21 10:32:26 -04:00
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printf("Delays calibrated\n");
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}
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static void adjust_phase(void)
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{
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2013-04-14 10:33:00 -04:00
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switch(dvisampler0_data0_cap_phase_read()) {
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2013-03-21 10:32:26 -04:00
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case DVISAMPLER_TOO_LATE:
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dvisampler0_data0_cap_dly_ctl_write(DVISAMPLER_DELAY_DEC);
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2013-05-09 04:52:43 -04:00
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dvisampler0_d0--;
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dvisampler0_data0_cap_phase_reset_write(1);
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2013-03-21 10:32:26 -04:00
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break;
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case DVISAMPLER_TOO_EARLY:
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dvisampler0_data0_cap_dly_ctl_write(DVISAMPLER_DELAY_INC);
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2013-05-09 04:52:43 -04:00
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dvisampler0_d0++;
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2013-04-14 10:33:00 -04:00
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dvisampler0_data0_cap_phase_reset_write(1);
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break;
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}
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2013-04-14 10:33:00 -04:00
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switch(dvisampler0_data1_cap_phase_read()) {
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2013-03-21 10:32:26 -04:00
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case DVISAMPLER_TOO_LATE:
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dvisampler0_data1_cap_dly_ctl_write(DVISAMPLER_DELAY_DEC);
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2013-05-09 04:52:43 -04:00
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dvisampler0_d1--;
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2013-04-14 10:33:00 -04:00
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dvisampler0_data1_cap_phase_reset_write(1);
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break;
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case DVISAMPLER_TOO_EARLY:
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dvisampler0_data1_cap_dly_ctl_write(DVISAMPLER_DELAY_INC);
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2013-05-09 04:52:43 -04:00
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dvisampler0_d1++;
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2013-04-14 10:33:00 -04:00
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dvisampler0_data1_cap_phase_reset_write(1);
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2013-03-21 10:32:26 -04:00
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break;
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}
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2013-04-14 10:33:00 -04:00
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switch(dvisampler0_data2_cap_phase_read()) {
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2013-03-21 10:32:26 -04:00
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case DVISAMPLER_TOO_LATE:
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2013-04-14 10:33:00 -04:00
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dvisampler0_data2_cap_dly_ctl_write(DVISAMPLER_DELAY_DEC);
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2013-05-09 04:52:43 -04:00
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dvisampler0_d2--;
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2013-04-14 10:33:00 -04:00
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dvisampler0_data2_cap_phase_reset_write(1);
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2013-03-21 10:32:26 -04:00
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break;
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case DVISAMPLER_TOO_EARLY:
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2013-04-14 10:33:00 -04:00
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dvisampler0_data2_cap_dly_ctl_write(DVISAMPLER_DELAY_INC);
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2013-05-09 04:52:43 -04:00
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dvisampler0_d2++;
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2013-04-14 10:33:00 -04:00
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dvisampler0_data2_cap_phase_reset_write(1);
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2013-03-21 10:32:26 -04:00
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break;
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}
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2013-03-23 19:46:23 -04:00
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}
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static int init_phase(void)
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{
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int o_d0, o_d1, o_d2;
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2013-03-23 19:46:23 -04:00
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int i, j;
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for(i=0;i<100;i++) {
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2013-05-09 04:52:43 -04:00
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o_d0 = dvisampler0_d0;
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o_d1 = dvisampler0_d1;
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o_d2 = dvisampler0_d2;
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2013-03-23 19:46:23 -04:00
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for(j=0;j<1000;j++)
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adjust_phase();
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2013-05-09 04:52:43 -04:00
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if((abs(dvisampler0_d0 - o_d0) < 4) && (abs(dvisampler0_d1 - o_d1) < 4) && (abs(dvisampler0_d2 - o_d2) < 4))
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2013-03-23 19:46:23 -04:00
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return 1;
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}
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return 0;
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2013-03-21 10:32:26 -04:00
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}
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2013-05-09 04:52:43 -04:00
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#define FRAMEBUFFER_COUNT 4
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#define FRAMEBUFFER_MASK (FRAMEBUFFER_COUNT - 1)
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static unsigned int dvisampler0_framebuffers[FRAMEBUFFER_COUNT][640*480] __attribute__((aligned(16)));
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static int dvisampler0_fb_slot_indexes[2];
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static int dvisampler0_next_fb_index;
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static void dvisampler0_init_video(void)
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{
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unsigned int mask;
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dvisampler0_dma_ev_pending_write(dvisampler0_dma_ev_pending_read());
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dvisampler0_dma_ev_enable_write(0x3);
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mask = irq_getmask();
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mask |= 1 << DVISAMPLER0_INTERRUPT;
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irq_setmask(mask);
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dvisampler0_dma_frame_size_write(sizeof(dvisampler0_framebuffers[0]));
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dvisampler0_fb_slot_indexes[0] = 0;
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dvisampler0_dma_slot0_address_write((unsigned int)dvisampler0_framebuffers[0]);
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dvisampler0_dma_slot0_status_write(DVISAMPLER_SLOT_LOADED);
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dvisampler0_fb_slot_indexes[1] = 1;
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dvisampler0_dma_slot1_address_write((unsigned int)dvisampler0_framebuffers[1]);
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dvisampler0_dma_slot1_status_write(DVISAMPLER_SLOT_LOADED);
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dvisampler0_next_fb_index = 2;
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fb_base_write((unsigned int)dvisampler0_framebuffers[0]);
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}
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void dvisampler0_isr(void)
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{
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int fb_index = -1;
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if(dvisampler0_dma_slot0_status_read() == DVISAMPLER_SLOT_PENDING) {
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fb_index = dvisampler0_fb_slot_indexes[0];
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dvisampler0_fb_slot_indexes[0] = dvisampler0_next_fb_index;
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dvisampler0_dma_slot0_address_write((unsigned int)dvisampler0_framebuffers[dvisampler0_next_fb_index]);
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dvisampler0_dma_slot0_status_write(DVISAMPLER_SLOT_LOADED);
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dvisampler0_next_fb_index = (dvisampler0_next_fb_index + 1) & FRAMEBUFFER_MASK;
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}
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if(dvisampler0_dma_slot1_status_read() == DVISAMPLER_SLOT_PENDING) {
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fb_index = dvisampler0_fb_slot_indexes[1];
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dvisampler0_fb_slot_indexes[1] = dvisampler0_next_fb_index;
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dvisampler0_dma_slot1_address_write((unsigned int)dvisampler0_framebuffers[dvisampler0_next_fb_index]);
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dvisampler0_dma_slot1_status_write(DVISAMPLER_SLOT_LOADED);
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dvisampler0_next_fb_index = (dvisampler0_next_fb_index + 1) & FRAMEBUFFER_MASK;
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}
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if(fb_index != -1)
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fb_base_write((unsigned int)dvisampler0_framebuffers[fb_index]);
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}
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2013-03-21 10:32:26 -04:00
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static void vmix(void)
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{
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unsigned int counter;
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while(1) {
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2013-04-14 10:33:00 -04:00
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while(!dvisampler0_clocking_locked_read());
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2013-03-21 10:32:26 -04:00
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printf("PLL locked\n");
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calibrate_delays();
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2013-03-23 19:46:23 -04:00
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if(init_phase())
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printf("Phase init OK\n");
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else
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printf("Phase did not settle\n");
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print_status();
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2013-03-21 10:32:26 -04:00
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counter = 0;
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2013-04-14 10:33:00 -04:00
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while(dvisampler0_clocking_locked_read()) {
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2013-03-21 10:32:26 -04:00
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counter++;
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2013-03-23 19:46:23 -04:00
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if(counter == 2000000) {
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print_status();
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2013-05-05 05:58:43 -04:00
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adjust_phase();
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2013-03-21 10:32:26 -04:00
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counter = 0;
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}
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}
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printf("PLL unlocked\n");
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}
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}
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2013-03-21 05:42:31 -04:00
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int main(void)
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{
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irq_setmask(0);
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irq_setie(1);
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uart_init();
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puts("Minimal video mixer software built "__DATE__" "__TIME__"\n");
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2013-05-09 04:52:43 -04:00
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dvisampler0_init_video();
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2013-05-06 03:56:49 -04:00
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fb_enable_write(1);
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2013-03-21 10:32:26 -04:00
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vmix();
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2013-03-21 05:42:31 -04:00
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return 0;
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}
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