2012-08-12 08:38:49 -04:00
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[> migScope
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------------
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2012-08-12 08:41:17 -04:00
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This is a small Logic Analyser to be embedded in a Fpga design to debug internal
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2012-08-12 19:02:38 -04:00
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or external signals.
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2012-08-12 08:38:49 -04:00
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[> Status:
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Early development phase
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2012-09-09 17:46:26 -04:00
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Simulation:
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-tb_spi2Csr : Test Spi <--> Csr Bridge : [Ok]
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-tb_TriggerCsr : Test Trigger with Csr : [Ok]
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-tb_RecorderCsr : Test Recorder with Csr : [Ok]
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-tb_MigScope : Global Test with Csr : [Ok]
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Example Design:
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2012-09-16 05:51:03 -04:00
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-de0_nano : Generate Signals in FPGA and probe them with migScope : [Ok]
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2012-09-12 12:09:12 -04:00
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Toolchain [Ok]
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2012-09-16 05:51:03 -04:00
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-de1 : Generate Signals in FPGA and probe them with migScope : [Ok]
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2012-09-12 12:09:12 -04:00
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Toolchain [Ok]
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2012-09-14 18:57:52 -04:00
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- test_MigIo : Led & Switch Test controlled by Python [Ok]
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2012-09-16 05:51:03 -04:00
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- test_MigLa : Logic Analyzer controlled by Python [Ok]
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2012-09-09 17:46:26 -04:00
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2012-08-12 08:38:49 -04:00
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[> Contact
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E-mail: florent@enjoy-digital.fr
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