2011-12-13 08:10:56 -05:00
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from migen.fhdl import verilog
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from migen.bus import wishbone
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2012-01-28 17:18:21 -05:00
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m1 = wishbone.Master()
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m2 = wishbone.Master()
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s1 = wishbone.Slave()
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s2 = wishbone.Slave()
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2011-12-13 08:10:56 -05:00
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wishbonecon0 = wishbone.InterconnectShared(
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[m1, m2],
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[(0, s1), (1, s2)],
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register=True,
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offset=1)
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2011-12-16 10:02:55 -05:00
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frag = wishbonecon0.get_fragment()
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2012-01-05 13:27:33 -05:00
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v = verilog.convert(frag, name="intercon", ios={m1.cyc_o, m1.stb_o, m1.we_o, m1.adr_o, m1.sel_o, m1.dat_o, m1.dat_i, m1.ack_i,
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2011-12-13 08:10:56 -05:00
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m2.cyc_o, m2.stb_o, m2.we_o, m2.adr_o, m2.sel_o, m2.dat_o, m2.dat_i, m2.ack_i,
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s1.cyc_i, s1.stb_i, s1.we_i, s1.adr_i, s1.sel_i, s1.dat_i, s1.dat_o, s1.ack_o,
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s2.cyc_i, s2.stb_i, s2.we_i, s2.adr_i, s2.sel_i, s2.dat_i, s2.dat_o, s2.ack_o})
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print(v)
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