litex/migen/build/platforms/sim.py

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from migen.build.generic_platform import *
from migen.build.sim import SimPlatform
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class SimPins(Pins):
def __init__(self, n):
Pins.__init__(self, "s "*n)
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_io = [
("sys_clk", 0, SimPins(1)),
("sys_rst", 0, SimPins(1)),
("serial", 0,
Subsignal("source_stb", SimPins(1)),
Subsignal("source_ack", SimPins(1)),
Subsignal("source_data", SimPins(8)),
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Subsignal("sink_stb", SimPins(1)),
Subsignal("sink_ack", SimPins(1)),
Subsignal("sink_data", SimPins(8)),
),
("eth_clocks", 0,
Subsignal("none", SimPins(1)),
),
("eth", 0,
Subsignal("source_stb", SimPins(1)),
Subsignal("source_ack", SimPins(1)),
Subsignal("source_data", SimPins(8)),
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Subsignal("sink_stb", SimPins(1)),
Subsignal("sink_ack", SimPins(1)),
Subsignal("sink_data", SimPins(8)),
),
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]
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class Platform(SimPlatform):
is_sim = True
default_clk_name = "sys_clk"
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default_clk_period = 1000 # on modern computers simulate at ~ 1MHz
def __init__(self):
SimPlatform.__init__(self, "SIM", _io)
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def do_finalize(self, fragment):
pass