2011-12-22 18:36:07 -05:00
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from migen.fhdl import verilog
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from migen.flow.ala import *
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2012-01-06 11:24:05 -05:00
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from migen.flow.plumbing import *
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2011-12-22 18:36:07 -05:00
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2012-01-06 11:24:05 -05:00
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act = Adder(32)
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comb = Combinator(act.operands, ["a"], ["b"])
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outbuf = Buffer(act.result.template())
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frag = get_actor_fragments(act, comb, outbuf)
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stb_a = comb.sinks[0].stb
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ack_a = comb.sinks[0].ack
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stb_b = comb.sinks[1].stb
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ack_b = comb.sinks[1].ack
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stb_a.name = "stb_a_i"
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ack_a.name = "ack_a_o"
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stb_b.name = "stb_b_i"
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ack_b.name = "stb_b_o"
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a = comb.ins[0].a
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b = comb.ins[1].b
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a.name = "a"
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b.name = "b"
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print(verilog.convert(frag, ios={stb_a, ack_a, stb_b, ack_b, a, b}))
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