example: flow conversion

2011-12-23 00:36:07 +01:00 · 2011-12-23 00:36:07 +01:00 · 1ce4fbdb98
parent edf90870c2
commit 1ce4fbdb98
1 changed files with 6 additions and 0 deletions
--- a/examples/dataflow.py
+++ b/examples/dataflow.py
@ -0,0 +1,6 @@
+from migen.fhdl import verilog 
+from migen.flow.ala import *
+
+act = Divider(32)
+frag = act.get_control_fragment() + act.get_process_fragment()
+print(verilog.Convert(frag))