litex/migen/bus/csr.py

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from migen.fhdl.structure import *
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from migen.corelogic.misc import optree
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from migen.bus.simple import Simple
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_desc = [
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(True, "a", 14),
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(True, "we", 1),
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(True, "d", 8),
(False, "d", 8)
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]
class Master(Simple):
def __init__(self):
Simple.__init__(self, _desc, False)
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class Slave(Simple):
def __init__(self):
Simple.__init__(self, _desc, True)
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class Interconnect:
def __init__(self, master, slaves):
self.master = master
self.slaves = slaves
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def get_fragment(self):
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comb = []
for slave in self.slaves:
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comb.append(slave.a_i.eq(self.master.a_o))
comb.append(slave.we_i.eq(self.master.we_o))
comb.append(slave.d_i.eq(self.master.d_o))
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rb = optree('|', [slave.d_o for slave in self.slaves])
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comb.append(self.master.d_i.eq(rb))
return Fragment(comb)