litex/migen/bus/csr.py

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from migen.fhdl import structure as f
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from .simple import Simple
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_desc = [
(True, "a", 16),
(True, "we", 1),
(True, "d", 32),
(False, "d", 32)
]
class Master(Simple):
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def __init__(self, name=""):
Simple.__init__(self, _desc, False, name)
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class Slave(Simple):
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def __init__(self, name=""):
Simple.__init__(self, _desc, True, name)
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class Interconnect:
def __init__(self, master, slaves):
self.master = master
self.slaves = slaves
def GetFragment(self):
a = f.Assign
comb = []
rb = f.Constant(0, f.BV(32))
for slave in self.slaves:
comb.append(a(slave.a_i, self.master.a_o))
comb.append(a(slave.we_i, self.master.we_o))
comb.append(a(slave.d_i, self.master.d_o))
rb = rb | slave.d_o
comb.append(a(master.d_i, rb))
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return f.Fragment(comb)