Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Named buses

This commit is contained in:
Sebastien Bourdeauducq 2011-12-08 19:16:08 +01:00
parent 5720a51dad
commit 7c99e51b90
3 changed files with 12 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
migen/bus/csr.py
View File

@ -9,12 +9,12 @@ _desc = [
]
class Master(Simple):
def __init__(self):
Simple.__init__(self, _desc, False)
def __init__(self, name=""):
Simple.__init__(self, _desc, False, name)
class Slave(Simple):
def __init__(self):
Simple.__init__(self, _desc, True)
def __init__(self, name=""):
Simple.__init__(self, _desc, True, name)
class Interconnect:
def __init__(self, master, slaves):

6
migen/bus/simple.py
View File

@ -5,7 +5,7 @@ from migen.fhdl import structure as f
# 1) string: name
# 2) int: width
class Simple():
def __init__(self, desc, slave):
def __init__(self, desc, slave, name):
for signal in desc:
if signal[0] ^ slave:
suffix = "_o"
@ -13,5 +13,7 @@ class Simple():
suffix = "_i"
modules = self.__module__.split('.')
busname = modules[len(modules)-1]
if name:
busname += "_" + name
signame = signal[1]+suffix
setattr(self, signame, f.Signal(f.BV(signal[2]), busname+"_"+signame))
setattr(self, signame, f.Signal(f.BV(signal[2]), busname + "_" + signame))

8
migen/bus/wishbone.py
View File

@ -16,9 +16,9 @@ _desc = [
]
class Master(Simple):
def __init__(self):
Simple.__init__(self, _desc, False)
def __init__(self, name=""):
Simple.__init__(self, _desc, False, name)
class Slave(Simple):
def __init__(self):
Simple.__init__(self, _desc, True)
def __init__(self, name=""):
Simple.__init__(self, _desc, True, name)