2011-12-16 15:30:22 -05:00
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from migen.fhdl.structure import *
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2013-03-10 14:32:38 -04:00
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from migen.fhdl.module import Module
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2011-12-13 11:33:12 -05:00
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from migen.bus import wishbone
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2013-02-24 06:31:00 -05:00
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from migen.genlib.misc import timeline
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2011-12-13 11:33:12 -05:00
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2013-03-10 14:32:38 -04:00
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class NorFlash(Module):
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2011-12-13 11:33:12 -05:00
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def __init__(self, adr_width, rd_timing):
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2012-02-15 10:55:13 -05:00
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self.bus = wishbone.Interface()
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2012-11-29 17:38:04 -05:00
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self.adr = Signal(adr_width-1)
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self.d = Signal(16)
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2011-12-18 16:02:05 -05:00
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self.oe_n = Signal()
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self.we_n = Signal()
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self.ce_n = Signal()
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2011-12-13 11:33:12 -05:00
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2013-03-10 14:32:38 -04:00
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###
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self.comb += [self.oe_n.eq(0), self.we_n.eq(1),
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2011-12-16 16:25:26 -05:00
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self.ce_n.eq(0)]
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2013-03-10 14:32:38 -04:00
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self.sync += timeline(self.bus.cyc & self.bus.stb, [
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(0, [self.adr.eq(Cat(0, self.bus.adr[:adr_width-2]))]),
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(rd_timing, [
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2012-03-15 15:26:04 -04:00
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self.bus.dat_r[16:].eq(self.d),
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2013-03-10 14:32:38 -04:00
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self.adr.eq(Cat(1, self.bus.adr[:adr_width-2]))]),
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(2*rd_timing, [
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2012-03-15 15:26:04 -04:00
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self.bus.dat_r[:16].eq(self.d),
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self.bus.ack.eq(1)]),
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2013-03-10 14:32:38 -04:00
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(2*rd_timing + 1, [
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2012-03-15 15:26:04 -04:00
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self.bus.ack.eq(0)])
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])
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