2015-02-28 04:27:16 -05:00
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from misoclib.tools.litescope.common import *
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2015-02-18 17:35:41 -05:00
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from migen.flow.plumbing import Buffer
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2013-09-21 07:04:07 -04:00
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2015-01-27 06:02:59 -05:00
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class LiteScopeSubSamplerUnit(Module):
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def __init__(self, dw):
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self.sink = sink = Sink(data_layout(dw))
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self.source = source = Source(data_layout(dw))
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self.value = Signal(32)
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###
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self.submodules.counter = Counter(bits_sign=32)
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done = Signal()
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self.comb += [
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done.eq(self.counter.value >= self.value),
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Record.connect(sink, source),
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source.stb.eq(sink.stb & done),
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self.counter.ce.eq(source.ack),
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self.counter.reset.eq(source.stb & source.ack & done)
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]
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class LiteScopeSubSampler(LiteScopeSubSamplerUnit, AutoCSR):
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def __init__(self, dw):
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LiteScopeSubSamplerUnit.__init__(self, dw)
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self._value = CSRStorage(32)
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###
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self.comb += self.value.eq(self._value.storage)
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2015-01-25 10:23:40 -05:00
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class LiteScopeRunLengthEncoderUnit(Module):
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2015-02-19 04:42:13 -05:00
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def __init__(self, dw, length):
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self.dw = dw
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2013-09-22 06:35:46 -04:00
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self.length = length
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2015-01-25 07:41:09 -05:00
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self.sink = sink = Sink(data_layout(dw))
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self.source = source = Source(data_layout(dw))
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2014-09-24 16:09:11 -04:00
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2015-01-25 07:41:09 -05:00
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self.enable = Signal()
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2014-05-13 15:30:32 -04:00
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###
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2015-02-18 17:35:41 -05:00
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self.submodules.buf = buf = Buffer(sink.description)
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self.comb += Record.connect(sink, buf.d)
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2013-09-22 06:35:46 -04:00
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2015-02-18 17:35:41 -05:00
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self.submodules.counter = counter = Counter(max=length)
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counter_done = Signal()
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self.comb += counter_done.eq(counter.value == length-1)
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2013-09-22 06:35:46 -04:00
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2014-05-22 12:13:27 -04:00
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change = Signal()
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2015-02-18 17:35:41 -05:00
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self.comb += change.eq(
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sink.stb &
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(sink.data != buf.q.data)
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)
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2014-05-22 12:13:27 -04:00
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2015-02-18 17:35:41 -05:00
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self.submodules.fsm = fsm = FSM(reset_state="BYPASS")
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fsm.act("BYPASS",
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Record.connect(buf.q, source),
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counter.reset.eq(1),
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If(sink.stb & ~change,
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If(self.enable,
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NextState("COUNT")
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)
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)
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)
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fsm.act("COUNT",
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buf.q.ack.eq(1),
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counter.ce.eq(sink.stb),
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If(~self.enable,
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NextState("BYPASS")
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).Elif(change | counter_done,
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source.stb.eq(1),
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source.data[:flen(counter.value)].eq(counter.value),
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source.data[-1].eq(1), # Set RLE bit
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2015-02-19 05:34:20 -05:00
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buf.q.ack.eq(source.ack),
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If(source.ack,
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NextState("BYPASS")
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)
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2014-05-20 03:02:35 -04:00
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)
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)
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2015-01-25 10:23:40 -05:00
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class LiteScopeRunLengthEncoder(LiteScopeRunLengthEncoderUnit, AutoCSR):
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def __init__(self, dw, length=1024):
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LiteScopeRunLengthEncoderUnit.__init__(self, dw, length)
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self._enable = CSRStorage()
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2015-02-19 04:26:34 -05:00
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self.external_enable = Signal(reset=1)
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###
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2015-02-19 04:26:34 -05:00
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self.comb += self.enable.eq(self._enable.storage & self.external_enable)
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2013-09-22 06:35:46 -04:00
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2015-01-27 05:34:59 -05:00
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class LiteScopeRecorderUnit(Module):
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def __init__(self, dw, depth):
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self.dw = dw
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self.depth = depth
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2015-01-25 07:41:09 -05:00
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self.trigger_sink = trigger_sink = Sink(hit_layout())
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self.data_sink = data_sink = Sink(data_layout(dw))
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2015-01-27 05:34:59 -05:00
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self.trigger = Signal()
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self.qualifier = Signal()
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self.length = Signal(bits_for(depth))
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self.offset = Signal(bits_for(depth))
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self.done = Signal()
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self.post_hit = Signal()
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2015-01-27 05:34:59 -05:00
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self.source = Source(data_layout(dw))
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2013-09-21 07:04:07 -04:00
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###
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2015-01-25 07:41:09 -05:00
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fifo = InsertReset(SyncFIFO(data_layout(dw), depth, buffered=True))
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2013-09-21 07:04:07 -04:00
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self.submodules += fifo
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2014-05-13 15:30:32 -04:00
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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self.comb += [
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self.source.stb.eq(fifo.source.stb),
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self.source.data.eq(fifo.source.data)
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]
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fsm.act("IDLE",
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self.done.eq(1),
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If(self.trigger,
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NextState("PRE_HIT_RECORDING"),
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2014-08-01 04:36:15 -04:00
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fifo.reset.eq(1),
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),
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fifo.source.ack.eq(self.source.ack)
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)
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fsm.act("PRE_HIT_RECORDING",
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fifo.sink.stb.eq(data_sink.stb),
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fifo.sink.data.eq(data_sink.data),
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data_sink.ack.eq(fifo.sink.ack),
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2015-01-27 05:34:59 -05:00
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fifo.source.ack.eq(fifo.fifo.level >= self.offset),
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If(trigger_sink.stb & trigger_sink.hit, NextState("POST_HIT_RECORDING"))
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2014-05-13 15:30:32 -04:00
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)
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fsm.act("POST_HIT_RECORDING",
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self.post_hit.eq(1),
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If(self.qualifier,
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fifo.sink.stb.eq(trigger_sink.stb & trigger_sink.hit & data_sink.stb)
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).Else(
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fifo.sink.stb.eq(data_sink.stb)
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),
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fifo.sink.data.eq(data_sink.data),
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data_sink.ack.eq(fifo.sink.ack),
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2014-05-13 15:30:32 -04:00
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2015-01-27 05:34:59 -05:00
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If(~fifo.sink.ack | (fifo.fifo.level >= self.length), NextState("IDLE"))
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2014-05-13 15:30:32 -04:00
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)
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2015-01-27 05:34:59 -05:00
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class LiteScopeRecorder(LiteScopeRecorderUnit, AutoCSR):
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def __init__(self, dw, depth):
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LiteScopeRecorderUnit.__init__(self, dw, depth)
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self._trigger = CSR()
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self._qualifier = CSRStorage()
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2015-01-27 05:34:59 -05:00
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self._length = CSRStorage(bits_for(depth))
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self._offset = CSRStorage(bits_for(depth))
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self._done = CSRStatus()
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self._source_stb = CSRStatus()
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2015-02-24 11:58:54 -05:00
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self._source_ack = CSR()
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self._source_data = CSRStatus(dw)
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###
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self.comb += [
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self.trigger.eq(self._trigger.re),
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2015-01-27 14:14:07 -05:00
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self.qualifier.eq(self._qualifier.storage),
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self.length.eq(self._length.storage),
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self.offset.eq(self._offset.storage),
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self._done.status.eq(self.done),
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self._source_stb.status.eq(self.source.stb),
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self._source_data.status.eq(self.source.data),
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2015-02-24 11:58:54 -05:00
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self.source.ack.eq(self._source_ack.re)
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2015-01-27 05:34:59 -05:00
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]
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