litex/litescope/core/storage.py

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from litescope.common import *
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class LiteScopeSubSamplerUnit(Module):
def __init__(self, dw):
self.sink = sink = Sink(data_layout(dw))
self.source = source = Source(data_layout(dw))
self.value = Signal(32)
###
self.submodules.counter = Counter(bits_sign=32)
done = Signal()
self.comb += [
done.eq(self.counter.value >= self.value),
Record.connect(sink, source),
source.stb.eq(sink.stb & done),
self.counter.ce.eq(source.ack),
self.counter.reset.eq(source.stb & source.ack & done)
]
class LiteScopeSubSampler(LiteScopeSubSamplerUnit, AutoCSR):
def __init__(self, dw):
LiteScopeSubSamplerUnit.__init__(self, dw)
self._value = CSRStorage(32)
###
self.comb += self.value.eq(self._value.storage)
class LiteScopeRunLengthEncoderUnit(Module):
def __init__(self, dw, length=1024):
self.dw = dw
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self.length = length
self.sink = sink = Sink(data_layout(dw))
self.source = source = Source(data_layout(dw))
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self.enable = Signal()
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###
sink_d = Sink(data_layout(dw))
self.sync += If(sink.stb, sink_d.eq(sink))
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cnt = Signal(max=length)
cnt_inc = Signal()
cnt_reset = Signal()
cnt_max = Signal()
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self.sync += \
If(cnt_reset,
cnt.eq(1),
).Elif(cnt_inc,
cnt.eq(cnt+1)
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)
self.comb += cnt_max.eq(cnt == length)
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change = Signal()
self.comb += change.eq(sink.stb & (sink.dat != sink_d.dat))
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fsm = FSM(reset_state="BYPASS")
self.submodules += fsm
fsm.act("BYPASS",
Record.connect(sink_d, source),
cnt_reset.eq(1),
If(self.enable & ~change & sink.stb, NextState("COUNT"))
)
fsm.act("COUNT",
cnt_inc.eq(sink.stb),
If(change | cnt_max | ~self.enable,
source.stb.eq(1),
source.dat[dw-1].eq(1), # Set RLE bit
source.dat[:flen(cnt)].eq(cnt),
NextState("BYPASS")
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)
)
class LiteScopeRunLengthEncoder(LiteScopeRunLengthEncoderUnit, AutoCSR):
def __init__(self, dw, length=1024):
LiteScopeRunLengthEncoderUnit.__init__(self, dw, length)
self._enable = CSRStorage()
###
self.comb += self.enable.eq(self_enable.storage)
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class LiteScopeRecorderUnit(Module):
def __init__(self, dw, depth):
self.dw = dw
self.depth = depth
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self.trigger_sink = trigger_sink = Sink(hit_layout())
self.data_sink = data_sink = Sink(data_layout(dw))
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self.trigger = Signal()
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self.qualifier = Signal()
self.length = Signal(bits_for(depth))
self.offset = Signal(bits_for(depth))
self.done = Signal()
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self.source = Source(data_layout(dw))
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###
fifo = InsertReset(SyncFIFO(data_layout(dw), depth, buffered=True))
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self.submodules += fifo
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fsm = FSM(reset_state="IDLE")
self.submodules += fsm
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self.comb += [
self.source.stb.eq(fifo.source.stb),
self.source.data.eq(fifo.source.data)
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]
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fsm.act("IDLE",
self.done.eq(1),
If(self.trigger,
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NextState("PRE_HIT_RECORDING"),
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fifo.reset.eq(1),
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),
fifo.source.ack.eq(self.source.ack)
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)
fsm.act("PRE_HIT_RECORDING",
fifo.sink.stb.eq(data_sink.stb),
fifo.sink.data.eq(data_sink.data),
data_sink.ack.eq(fifo.sink.ack),
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fifo.source.ack.eq(fifo.fifo.level >= self.offset),
If(trigger_sink.stb & trigger_sink.hit, NextState("POST_HIT_RECORDING"))
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)
fsm.act("POST_HIT_RECORDING",
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If(self.qualifier,
fifo.sink.stb.eq(trigger_sink.stb & trigger_sink.hit & data_sink.stb)
).Else(
fifo.sink.stb.eq(data_sink.stb)
),
fifo.sink.data.eq(data_sink.data),
data_sink.ack.eq(fifo.sink.ack),
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If(~fifo.sink.ack | (fifo.fifo.level >= self.length), NextState("IDLE"))
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)
class LiteScopeRecorder(LiteScopeRecorderUnit, AutoCSR):
def __init__(self, dw, depth):
LiteScopeRecorderUnit.__init__(self, dw, depth)
self._trigger = CSR()
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self._qualifier = CSRStorage()
self._length = CSRStorage(bits_for(depth))
self._offset = CSRStorage(bits_for(depth))
self._done = CSRStatus()
self._source_stb = CSRStatus()
self._source_ack = CSR()
self._source_data = CSRStatus(dw)
###
self.comb += [
self.trigger.eq(self._trigger.re),
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self.qualifier.eq(self._qualifier.storage),
self.length.eq(self._length.storage),
self.offset.eq(self._offset.storage),
self._done.status.eq(self.done),
self._source_stb.status.eq(self.source.stb),
self._source_data.status.eq(self.source.data),
self.source.ack.eq(self._source_ack.re)
]