litex/liteeth/core/etherbone/record.py

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from liteeth.common import *
from liteeth.generic import *
from liteeth.generic.depacketizer import LiteEthDepacketizer
from liteeth.generic.packetizer import LiteEthPacketizer
class LiteEthEtherboneRecordPacketizer(LiteEthPacketizer):
def __init__(self):
LiteEthPacketizer.__init__(self,
eth_etherbone_record_description(32),
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eth_etherbone_packet_user_description(32),
etherbone_record_header,
etherbone_record_header_len)
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class LiteEthEtherboneRecordDepacketizer(LiteEthDepacketizer):
def __init__(self):
LiteEthDepacketizer.__init__(self,
eth_etherbone_packet_user_description(32),
eth_etherbone_record_description(32),
etherbone_record_header,
etherbone_record_header_len)
class LiteEthEtherboneRecordReceiver(Module):
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def __init__(self, buffer_depth=256):
self.sink = sink = Sink(eth_etherbone_record_description(32))
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self.source = source = Source(eth_etherbone_mmap_description(32))
###
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fifo = SyncFIFO(eth_etherbone_record_description(32), buffer_depth, buffered=True)
self.submodules += fifo
self.comb += Record.connect(sink, fifo.sink)
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self.submodules.base_addr = base_addr = FlipFlop(32)
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self.comb += base_addr.d.eq(fifo.source.data)
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self.submodules.counter = counter = Counter(max=512)
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
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fifo.source.ack.eq(1),
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counter.reset.eq(1),
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If(fifo.source.stb & fifo.source.sop,
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base_addr.ce.eq(1),
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If(fifo.source.wcount,
NextState("RECEIVE_WRITES")
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).Elif(fifo.source.rcount,
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NextState("RECEIVE_READS")
)
)
)
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fsm.act("RECEIVE_WRITES",
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source.stb.eq(fifo.source.stb),
source.sop.eq(counter.value == 0),
source.eop.eq(counter.value == fifo.source.wcount-1),
source.count.eq(fifo.source.wcount),
source.be.eq(fifo.source.byte_enable),
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source.addr.eq(base_addr.q[2:] + counter.value),
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source.we.eq(1),
source.data.eq(fifo.source.data),
fifo.source.ack.eq(source.ack),
If(source.stb & source.ack,
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counter.ce.eq(1),
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If(source.eop,
If(fifo.source.rcount,
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NextState("RECEIVE_BASE_RET_ADDR")
).Else(
NextState("IDLE")
)
)
)
)
fsm.act("RECEIVE_BASE_RET_ADDR",
counter.reset.eq(1),
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If(fifo.source.stb & fifo.source.sop,
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base_addr.ce.eq(1),
NextState("RECEIVE_READS")
)
)
fsm.act("RECEIVE_READS",
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source.stb.eq(fifo.source.stb),
source.sop.eq(counter.value == 0),
source.eop.eq(counter.value == fifo.source.rcount-1),
source.count.eq(fifo.source.rcount),
source.base_addr.eq(base_addr.q),
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source.addr.eq(fifo.source.data[2:]),
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fifo.source.ack.eq(source.ack),
If(source.stb & source.ack,
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counter.ce.eq(1),
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If(source.eop,
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NextState("IDLE")
)
)
)
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class LiteEthEtherboneRecordSender(Module):
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def __init__(self, buffer_depth=256):
self.sink = sink = Sink(eth_etherbone_mmap_description(32))
self.source = source = Source(eth_etherbone_record_description(32))
###
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pbuffer = PacketBuffer(eth_etherbone_mmap_description(32), buffer_depth)
self.submodules += pbuffer
self.comb += Record.connect(sink, pbuffer.sink)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
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pbuffer.source.ack.eq(1),
If(pbuffer.source.stb & pbuffer.source.sop,
pbuffer.source.ack.eq(0),
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NextState("SEND_BASE_ADDRESS")
)
)
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self.comb += [
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source.byte_enable.eq(pbuffer.source.be),
If(pbuffer.source.we,
source.wcount.eq(pbuffer.source.count)
).Else(
source.rcount.eq(pbuffer.source.count)
)
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]
fsm.act("SEND_BASE_ADDRESS",
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source.stb.eq(pbuffer.source.stb),
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source.sop.eq(1),
source.eop.eq(0),
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source.data.eq(pbuffer.source.base_addr),
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If(source.ack,
NextState("SEND_DATA")
)
)
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fsm.act("SEND_DATA",
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source.stb.eq(pbuffer.source.stb),
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source.sop.eq(0),
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source.eop.eq(pbuffer.source.eop),
source.data.eq(pbuffer.source.data),
If(source.stb & source.ack,
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pbuffer.source.ack.eq(1),
If(source.eop,
NextState("IDLE")
)
)
)
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# Limitation: For simplicity we only support 1 record per packet
class LiteEthEtherboneRecord(Module):
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def __init__(self, endianness="big"):
self.sink = sink = Sink(eth_etherbone_packet_user_description(32))
self.source = source = Sink(eth_etherbone_packet_user_description(32))
###
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# receive record, decode it and generate mmap stream
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self.submodules.depacketizer = depacketizer = LiteEthEtherboneRecordDepacketizer()
self.submodules.receiver = receiver = LiteEthEtherboneRecordReceiver()
self.comb += [
Record.connect(sink, depacketizer.sink),
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Record.connect(depacketizer.source, receiver.sink)
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]
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if endianness is "big":
self.comb += receiver.sink.data.eq(reverse_bytes(depacketizer.source.data))
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# save last ip address
last_ip_address = Signal(32)
self.sync += [
If(sink.stb & sink.sop & sink.ack,
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last_ip_address.eq(sink.ip_address)
)
]
# receive mmap stream, encode it and send records
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self.submodules.sender = sender = LiteEthEtherboneRecordSender()
self.submodules.packetizer = packetizer = LiteEthEtherboneRecordPacketizer()
self.comb += [
Record.connect(sender.source, packetizer.sink),
Record.connect(packetizer.source, source),
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source.length.eq(sender.source.wcount*4 + 4 +etherbone_record_header_len), # XXX improve this
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source.ip_address.eq(last_ip_address)
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]
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if endianness is "big":
self.comb += packetizer.sink.data.eq(reverse_bytes(sender.source.data))