litex/misoclib/cpu/peripherals/identifier/__init__.py

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from migen.fhdl.std import *
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from migen.bank.description import *
from misoclib.cpu.peripherals.identifier import git
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class Identifier(Module, AutoCSR):
def __init__(self, sysid, frequency, revision=None):
self._sysid = CSRStatus(16)
self._revision = CSRStatus(32)
self._frequency = CSRStatus(32)
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###
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if revision is None:
revision = git.get_id()
self.comb += [
self._sysid.status.eq(sysid),
self._revision.status.eq(revision),
self._frequency.status.eq(frequency)
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]