2012-06-12 15:04:47 -04:00
|
|
|
from migen.fhdl.structure import *
|
2013-04-10 13:12:42 -04:00
|
|
|
from migen.fhdl.module import Module
|
2012-06-12 15:04:47 -04:00
|
|
|
from migen.flow.actor import *
|
2013-02-22 17:19:37 -05:00
|
|
|
from migen.genlib.buffers import ReorderBuffer
|
2012-06-12 15:04:47 -04:00
|
|
|
|
2013-04-10 13:12:42 -04:00
|
|
|
class SequentialReader(Module):
|
2012-06-12 15:04:47 -04:00
|
|
|
def __init__(self, port):
|
2013-04-10 13:12:42 -04:00
|
|
|
assert(len(port.slots) == 1)
|
|
|
|
self.address = Sink([("a", port.hub.aw)])
|
|
|
|
self.data = Source([("d", port.hub.dw)])
|
|
|
|
self.busy = Signal()
|
2012-06-12 15:04:47 -04:00
|
|
|
|
2013-04-10 13:12:42 -04:00
|
|
|
###
|
|
|
|
|
2012-06-12 15:04:47 -04:00
|
|
|
sample = Signal()
|
|
|
|
data_reg_loaded = Signal()
|
2013-04-10 13:12:42 -04:00
|
|
|
data_reg = Signal(port.hub.dw)
|
2012-06-12 15:04:47 -04:00
|
|
|
accept_new = Signal()
|
|
|
|
|
2013-04-10 13:12:42 -04:00
|
|
|
# We check that len(port.slots) == 1
|
|
|
|
# and therefore we can assume that port.ack
|
2012-06-12 15:04:47 -04:00
|
|
|
# goes low until the data phase.
|
|
|
|
|
2013-04-10 13:12:42 -04:00
|
|
|
self.comb += [
|
|
|
|
self.busy.eq(~data_reg_loaded | ~port.ack),
|
|
|
|
port.adr.eq(self.address.payload.a),
|
|
|
|
port.we.eq(0),
|
|
|
|
accept_new.eq(~data_reg_loaded | self.data.ack),
|
|
|
|
port.stb.eq(self.address.stb & accept_new),
|
|
|
|
self.address.ack.eq(port.ack & accept_new),
|
|
|
|
self.data.stb.eq(data_reg_loaded),
|
|
|
|
self.data.payload.d.eq(data_reg)
|
2012-06-12 15:04:47 -04:00
|
|
|
]
|
2013-04-10 13:12:42 -04:00
|
|
|
self.sync += [
|
|
|
|
If(self.data.ack, data_reg_loaded.eq(0)),
|
2012-06-12 15:04:47 -04:00
|
|
|
If(sample,
|
|
|
|
data_reg_loaded.eq(1),
|
2013-04-10 13:12:42 -04:00
|
|
|
data_reg.eq(port.dat_r)
|
2012-06-12 15:04:47 -04:00
|
|
|
),
|
2013-04-10 13:12:42 -04:00
|
|
|
sample.eq(port.get_call_expression())
|
2012-06-12 15:04:47 -04:00
|
|
|
]
|
2012-07-12 12:34:13 -04:00
|
|
|
|
2013-04-10 13:12:42 -04:00
|
|
|
class OOOReader(Module):
|
2012-07-12 12:34:13 -04:00
|
|
|
def __init__(self, port):
|
2013-04-10 13:12:42 -04:00
|
|
|
assert(len(port.slots) > 1)
|
|
|
|
self.address = Sink([("a", port.hub.aw)])
|
|
|
|
self.data = Source([("d", port.hub.dw)])
|
|
|
|
self.busy = Signal() # TODO: drive busy
|
2012-07-12 12:34:13 -04:00
|
|
|
|
2013-04-10 13:12:42 -04:00
|
|
|
###
|
|
|
|
|
|
|
|
tag_width = len(port.tag_call)
|
|
|
|
data_width = port.hub.dw
|
|
|
|
depth = len(port.slots)
|
2012-07-12 12:34:13 -04:00
|
|
|
rob = ReorderBuffer(tag_width, data_width, depth)
|
2013-04-10 13:12:42 -04:00
|
|
|
self.submodules += rob
|
2012-07-12 12:34:13 -04:00
|
|
|
|
2013-04-10 13:12:42 -04:00
|
|
|
self.comb += [
|
|
|
|
port.adr.eq(self.address.payload.a),
|
|
|
|
port.we.eq(0),
|
|
|
|
port.stb.eq(self.address.stb & rob.can_issue),
|
|
|
|
self.address.ack.eq(port.ack & rob.can_issue),
|
|
|
|
rob.issue.eq(self.address.stb & port.ack),
|
|
|
|
rob.tag_issue.eq(port.base + port.tag_issue),
|
2012-07-12 12:34:13 -04:00
|
|
|
|
2013-04-10 13:12:42 -04:00
|
|
|
rob.data_call.eq(port.dat_r),
|
2012-07-12 12:34:13 -04:00
|
|
|
|
2013-04-10 13:12:42 -04:00
|
|
|
self.data.stb.eq(rob.can_read),
|
|
|
|
rob.read.eq(self.data.ack),
|
|
|
|
self.data.payload.d.eq(rob.data_read)
|
2012-07-12 12:34:13 -04:00
|
|
|
]
|
2013-04-10 13:12:42 -04:00
|
|
|
self.sync += [
|
2012-07-12 12:34:13 -04:00
|
|
|
# Data is announced one cycle in advance.
|
|
|
|
# Register the call to synchronize it with the data signal.
|
2013-04-10 13:12:42 -04:00
|
|
|
rob.call.eq(port.call),
|
|
|
|
rob.tag_call.eq(port.tag_call)
|
2012-07-12 12:34:13 -04:00
|
|
|
]
|
|
|
|
|
2013-04-28 12:06:36 -04:00
|
|
|
class SequentialWriter(Module):
|
|
|
|
def __init__(self, port):
|
|
|
|
assert(len(port.slots) == 1)
|
|
|
|
self.address_data = Sink([("a", port.hub.aw), ("d", port.hub.dw)])
|
|
|
|
self.busy = Signal()
|
|
|
|
|
|
|
|
###
|
|
|
|
|
|
|
|
data_reg = Signal(port.hub.dw)
|
|
|
|
self.comb += [
|
|
|
|
port.adr.eq(self.address_data.payload.a),
|
|
|
|
port.we.eq(1),
|
|
|
|
port.stb.eq(self.address_data.stb),
|
2013-05-01 15:52:26 -04:00
|
|
|
self.address_data.ack.eq(port.ack),
|
|
|
|
port.dat_wm.eq(0)
|
2013-04-28 12:06:36 -04:00
|
|
|
]
|
|
|
|
self.sync += [
|
|
|
|
port.dat_w.eq(0),
|
|
|
|
If(port.get_call_expression(),
|
|
|
|
self.busy.eq(0),
|
|
|
|
port.dat_w.eq(data_reg)
|
|
|
|
),
|
|
|
|
If(self.address_data.stb & self.address_data.ack,
|
|
|
|
self.busy.eq(1),
|
|
|
|
data_reg.eq(self.address_data.payload.d)
|
|
|
|
)
|
|
|
|
]
|
|
|
|
|
|
|
|
class _WriteSlot(Module):
|
2013-05-04 11:38:17 -04:00
|
|
|
def __init__(self, port, load_data, n):
|
2013-04-28 12:06:36 -04:00
|
|
|
self.busy = Signal()
|
|
|
|
|
|
|
|
###
|
|
|
|
|
|
|
|
drive_data = Signal()
|
|
|
|
data_reg = Signal(port.hub.dw)
|
2013-05-01 15:52:26 -04:00
|
|
|
self.comb += [
|
|
|
|
If(drive_data, port.dat_w.eq(data_reg)),
|
|
|
|
port.dat_wm.eq(0)
|
|
|
|
]
|
2013-04-28 12:06:36 -04:00
|
|
|
|
|
|
|
self.sync += [
|
|
|
|
drive_data.eq(0),
|
|
|
|
If(port.get_call_expression(n),
|
|
|
|
self.busy.eq(0),
|
|
|
|
drive_data.eq(1)
|
2013-05-04 11:38:17 -04:00
|
|
|
),
|
|
|
|
If(port.stb & port.ack & (port.tag_issue == n),
|
|
|
|
self.busy.eq(1),
|
|
|
|
data_reg.eq(load_data)
|
|
|
|
),
|
2013-04-28 12:06:36 -04:00
|
|
|
]
|
|
|
|
|
|
|
|
class OOOWriter(Module):
|
|
|
|
def __init__(self, port):
|
|
|
|
assert(len(port.slots) > 1)
|
|
|
|
self.address_data = Sink([("a", port.hub.aw), ("d", port.hub.dw)])
|
|
|
|
self.busy = Signal()
|
|
|
|
|
|
|
|
###
|
|
|
|
|
|
|
|
self.comb += [
|
|
|
|
port.adr.eq(self.address_data.payload.a),
|
|
|
|
port.we.eq(1),
|
|
|
|
port.stb.eq(self.address_data.stb),
|
|
|
|
self.address_data.ack.eq(port.ack)
|
|
|
|
]
|
|
|
|
|
|
|
|
busy = 0
|
|
|
|
for i in range(len(port.slots)):
|
2013-05-04 11:38:17 -04:00
|
|
|
write_slot = _WriteSlot(port, self.address_data.payload.d, i)
|
|
|
|
#write_slot = _WriteSlot(port, 0x12345678abad1deacafebabedeadbeef, i)
|
2013-04-28 12:06:36 -04:00
|
|
|
self.submodules += write_slot
|
|
|
|
busy = busy | write_slot.busy
|
|
|
|
self.comb += self.busy.eq(busy)
|
|
|
|
|
2013-04-10 13:12:42 -04:00
|
|
|
def Reader(port):
|
|
|
|
if len(port.slots) == 1:
|
|
|
|
return SequentialReader(port)
|
|
|
|
else:
|
|
|
|
return OOOReader(port)
|
2013-04-28 12:06:36 -04:00
|
|
|
|
|
|
|
def Writer(port):
|
|
|
|
if len(port.slots) == 1:
|
|
|
|
return SequentialWriter(port)
|
|
|
|
else:
|
|
|
|
return OOOWriter(port)
|