2015-02-21 17:13:43 -05:00
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from migen.fhdl.std import *
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from migen.flow.actor import *
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2015-03-22 05:56:29 -04:00
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from misoclib.com.liteusb.common import *
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2015-03-22 06:08:47 -04:00
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from misoclib.com.liteusb.frontend.crossbar import LiteUSBCrossbar
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from misoclib.com.liteusb.core.packetizer import LiteUSBPacketizer
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from misoclib.com.liteusb.core.depacketizer import LiteUSBDepacketizer
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2015-02-21 17:13:43 -05:00
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2015-04-13 08:27:31 -04:00
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2015-03-22 06:08:47 -04:00
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class LiteUSBCom(Module):
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2015-04-13 08:09:58 -04:00
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def __init__(self, phy, *ports):
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# crossbar
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self.submodules.crossbar = LiteUSBCrossbar(list(ports))
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2015-02-21 17:13:43 -05:00
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2015-04-13 08:09:58 -04:00
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# packetizer / depacketizer
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self.submodules.packetizer = LiteUSBPacketizer()
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self.submodules.depacketizer = LiteUSBDepacketizer()
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self.comb += [
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self.crossbar.slave.source.connect(self.packetizer.sink),
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self.depacketizer.source.connect(self.crossbar.slave.sink)
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]
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2015-02-21 17:13:43 -05:00
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2015-04-13 08:09:58 -04:00
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# phy
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self.comb += [
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self.packetizer.source.connect(phy.sink),
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phy.source.connect(self.depacketizer.sink)
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]
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