2015-09-22 12:36:47 -04:00
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from migen import *
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2015-02-27 10:55:27 -05:00
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from migen.bus.transactions import *
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from migen.sim.generic import run_simulation
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2015-09-22 12:35:02 -04:00
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from misoc.mem.sdram.core import lasmibus
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2015-02-27 10:55:27 -05:00
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2015-04-13 10:47:22 -04:00
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2015-02-27 10:55:27 -05:00
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def my_generator(n):
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2015-04-13 10:19:55 -04:00
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bank = n % 4
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for x in range(4):
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t = TWrite(4*bank+x, 0x1000*bank + 0x100*x)
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yield t
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print("{0}: Wrote in {1} cycle(s)".format(n, t.latency))
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2015-02-27 10:55:27 -05:00
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2015-04-13 10:19:55 -04:00
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for x in range(4):
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t = TRead(4*bank+x)
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yield t
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print("{0}: Read {1:x} in {2} cycle(s)".format(n, t.data, t.latency))
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assert(t.data == 0x1000*bank + 0x100*x)
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2015-02-27 10:55:27 -05:00
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2015-04-13 10:47:22 -04:00
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2015-02-27 10:55:27 -05:00
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class MyModel(lasmibus.TargetModel):
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2015-04-13 10:19:55 -04:00
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def read(self, bank, address):
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r = 0x1000*bank + 0x100*address
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#print("read from bank {0} address {1} -> {2:x}".format(bank, address, r))
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return r
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2015-02-27 10:55:27 -05:00
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2015-04-13 10:19:55 -04:00
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def write(self, bank, address, data, we):
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print("write to bank {0} address {1:x} data {2:x}".format(bank, address, data))
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assert(data == 0x1000*bank + 0x100*address)
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2015-02-27 10:55:27 -05:00
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2015-04-13 10:47:22 -04:00
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2015-02-27 10:55:27 -05:00
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class TB(Module):
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2015-04-13 10:19:55 -04:00
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def __init__(self):
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self.submodules.controller = lasmibus.Target(MyModel(), aw=4, dw=32, nbanks=4, req_queue_size=4,
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read_latency=4, write_latency=1)
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self.submodules.xbar = lasmibus.Crossbar([self.controller.bus], 2)
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self.initiators = [lasmibus.Initiator(my_generator(n), self.xbar.get_master()) for n in range(4)]
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self.submodules += self.initiators
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2015-02-27 10:55:27 -05:00
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if __name__ == "__main__":
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2015-04-13 10:19:55 -04:00
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run_simulation(TB())
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