2015-09-22 12:36:47 -04:00
|
|
|
from migen import *
|
2015-03-17 14:08:31 -04:00
|
|
|
from migen.bus import wishbone
|
|
|
|
from migen.genlib.io import CRG
|
|
|
|
|
2015-09-22 12:35:02 -04:00
|
|
|
from misoc.soc import SoC
|
2015-03-17 14:08:31 -04:00
|
|
|
|
2015-04-13 10:47:22 -04:00
|
|
|
|
2015-03-17 14:08:31 -04:00
|
|
|
class BaseSoC(SoC):
|
2015-04-13 10:19:55 -04:00
|
|
|
default_platform = "versa"
|
|
|
|
def __init__(self, platform, **kwargs):
|
|
|
|
SoC.__init__(self, platform,
|
2015-04-13 11:56:51 -04:00
|
|
|
clk_freq=100*1000000,
|
|
|
|
integrated_rom_size=0x8000,
|
|
|
|
**kwargs)
|
2015-04-13 10:19:55 -04:00
|
|
|
self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst_n"))
|
|
|
|
self.comb += platform.request("user_led", 0).eq(ResetSignal())
|
2015-03-17 14:08:31 -04:00
|
|
|
|
|
|
|
default_subtarget = BaseSoC
|