2012-09-12 16:19:42 -04:00
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from migen.fhdl.structure import *
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from migen.bus import csr
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2013-04-14 12:23:37 -04:00
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from migen.bank import csrgen
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2012-09-12 16:19:42 -04:00
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from migen.bank.description import *
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2013-02-22 08:28:05 -05:00
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class MiIo:
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2012-09-17 11:00:47 -04:00
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#
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# Definition
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#
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2013-03-18 16:45:07 -04:00
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def __init__(self, address, width, mode="IO", interface=None):
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2012-09-13 07:14:27 -04:00
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self.address = address
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2012-09-12 16:19:42 -04:00
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self.width = width
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2013-03-18 16:45:07 -04:00
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self.mode = mode.upper()
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2012-09-14 06:57:09 -04:00
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self.interface = interface
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2013-03-18 16:45:07 -04:00
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self.words = int((2**bits_for(width-1))/8)
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2013-02-22 08:28:05 -05:00
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2012-09-12 16:19:42 -04:00
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if "I" in self.mode:
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2013-01-03 16:57:26 -05:00
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self.i = Signal(self.width)
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2013-04-14 12:23:37 -04:00
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self._r_i = CSRStatus(self.width)
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2013-02-22 08:28:05 -05:00
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2012-09-12 16:19:42 -04:00
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if "O" in self.mode:
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2013-01-03 16:57:26 -05:00
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self.o = Signal(self.width)
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2013-04-14 12:23:37 -04:00
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self._r_o = CSRStorage(self.width)
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2013-02-22 08:28:05 -05:00
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2013-03-26 17:14:25 -04:00
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self.bank = csrgen.Bank([self._r_o, self._r_i], address=self.address)
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2012-09-17 11:00:47 -04:00
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2012-09-12 16:19:42 -04:00
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def get_fragment(self):
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comb = []
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2013-02-22 08:28:05 -05:00
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2012-09-13 07:14:27 -04:00
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if "I" in self.mode:
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2013-04-14 12:23:37 -04:00
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comb += [self._r_i.status.eq(self.i)]
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2013-02-22 08:28:05 -05:00
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2012-09-13 07:14:27 -04:00
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if "O" in self.mode:
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2013-04-14 12:23:37 -04:00
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comb += [self.o.eq(self._r_o.storage)]
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2013-02-22 08:28:05 -05:00
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return Fragment(comb) + self.bank.get_fragment()
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2012-09-17 11:00:47 -04:00
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#
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2013-03-22 07:35:12 -04:00
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# Driver
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2012-09-17 11:00:47 -04:00
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#
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2013-03-22 07:35:12 -04:00
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def set(self, data):
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2013-03-21 07:23:44 -04:00
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self.interface.write(self.bank.get_base(), data)
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2012-09-17 11:00:47 -04:00
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2013-03-22 07:35:12 -04:00
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def get(self):
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2013-03-21 07:23:44 -04:00
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return self.interface.read(self.bank.get_base() + self.words)
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