litex/migen/corelogic/divider.py

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from migen.fhdl.structure import *
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class Divider:
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def __init__(self, w):
self.w = w
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self.start_i = Signal()
self.dividend_i = Signal(BV(w))
self.divisor_i = Signal(BV(w))
self.ready_o = Signal()
self.quotient_o = Signal(BV(w))
self.remainder_o = Signal(BV(w))
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def get_fragment(self):
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w = self.w
qr = Signal(BV(2*w))
counter = Signal(BV(bits_for(w)))
divisor_r = Signal(BV(w))
diff = Signal(BV(w+1))
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comb = [
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self.quotient_o.eq(qr[:w]),
self.remainder_o.eq(qr[w:]),
self.ready_o.eq(counter == Constant(0, counter.bv)),
diff.eq(self.remainder_o - divisor_r)
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]
sync = [
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If(self.start_i,
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counter.eq(w),
qr.eq(self.dividend_i),
divisor_r.eq(self.divisor_i)
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).Elif(~self.ready_o,
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If(diff[w],
qr.eq(Cat(0, qr[:2*w-1]))
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).Else(
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qr.eq(Cat(1, qr[:w-1], diff[:w]))
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),
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counter.eq(counter - Constant(1, counter.bv))
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)
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]
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return Fragment(comb, sync)