2012-08-12 08:38:49 -04:00
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[> migScope
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2012-08-12 08:41:17 -04:00
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This is a small Logic Analyser to be embedded in a Fpga design to debug internal
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2012-08-12 19:02:38 -04:00
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or external signals.
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2012-08-12 08:38:49 -04:00
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[> Status:
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Early development phase
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[> Contact
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E-mail: florent@enjoy-digital.fr
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