2013-09-03 18:01:33 -04:00
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from migen.fhdl.std import *
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from migen.flow.actor import *
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from migen.genlib import fifo
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2013-09-04 11:22:50 -04:00
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class _FIFOActor(Module):
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def __init__(self, fifo_class, layout, depth):
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2013-09-03 18:01:33 -04:00
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self.sink = Sink(layout)
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self.source = Source(layout)
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self.busy = Signal()
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2013-09-04 11:22:50 -04:00
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###
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2013-09-03 18:01:33 -04:00
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2013-09-04 11:22:50 -04:00
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self.submodules.fifo = fifo_class(layout, depth)
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2013-09-03 18:01:33 -04:00
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2013-09-04 11:22:50 -04:00
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self.comb += [
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self.sink.ack.eq(self.fifo.writable),
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2013-09-04 11:33:53 -04:00
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self.fifo.we.eq(self.sink.stb),
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2013-09-04 11:22:50 -04:00
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self.fifo.din.eq(self.sink.payload),
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2013-09-03 18:01:33 -04:00
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2013-09-04 11:22:50 -04:00
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self.source.stb.eq(self.fifo.readable),
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2014-10-20 11:11:59 -04:00
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self.source.eq(self.fifo.dout),
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2013-09-04 11:22:50 -04:00
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self.fifo.re.eq(self.source.ack)
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]
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2013-09-03 18:01:33 -04:00
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2013-09-04 11:22:50 -04:00
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class SyncFIFO(_FIFOActor):
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def __init__(self, layout, depth):
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_FIFOActor.__init__(self, fifo.SyncFIFO, layout, depth)
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2013-09-03 18:01:33 -04:00
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2013-09-04 11:22:50 -04:00
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class AsyncFIFO(_FIFOActor):
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def __init__(self, layout, depth):
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2014-10-20 11:11:59 -04:00
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_FIFOActor.__init__(self, fifo.AsyncFIFO, layout, depth)
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