2012-04-02 13:22:17 -04:00
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class Constraints:
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2012-06-17 07:41:26 -04:00
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def __init__(self, crg0, norflash0, uart0, ddrphy0, minimac0, fb0):
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2012-04-02 13:22:17 -04:00
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self.constraints = []
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def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
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self.constraints.append((signal, vec, pin, iostandard, extra))
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def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
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2012-11-29 17:38:04 -05:00
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assert(signal.nbits == len(pins))
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2012-04-02 13:22:17 -04:00
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i = 0
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for p in pins:
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add(signal, p, i, iostandard, extra)
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i += 1
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add(crg0.clkin, "AB11", extra="TNM_NET = \"GRPclk50\"")
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add(crg0.ac97_rst_n, "D6")
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add(crg0.videoin_rst_n, "W17")
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add(crg0.flash_rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
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add(crg0.trigger_reset, "AA4")
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2012-09-10 18:21:07 -04:00
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add(crg0.eth_clk_pad, "M20")
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2012-06-17 07:41:26 -04:00
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add(crg0.vga_clk_pad, "A11")
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2012-04-02 13:22:17 -04:00
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add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
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"F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20",
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"G19", "C22", "C20", "D22", "D21", "F19", "F18", "D20", "D19"],
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extra="SLEW = FAST | DRIVE = 8")
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add_vec(norflash0.d, ["AA20", "U14", "U13", "AA6", "AB6", "W4", "Y4", "Y7",
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"AA2", "AB2", "V15", "AA18", "AB18", "Y13", "AA12", "AB12"],
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extra="SLEW = FAST | DRIVE = 8 | PULLDOWN")
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add(norflash0.oe_n, "M22", extra="SLEW = FAST | DRIVE = 8")
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add(norflash0.we_n, "N20", extra="SLEW = FAST | DRIVE = 8")
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add(norflash0.ce_n, "M21", extra="SLEW = FAST | DRIVE = 8")
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add(uart0.tx, "L17", extra="SLEW = SLOW")
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add(uart0.rx, "K18", extra="PULLUP")
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ddrsettings = "IOSTANDARD = SSTL2_I"
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add(ddrphy0.sd_clk_out_p, "M3", extra=ddrsettings)
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add(ddrphy0.sd_clk_out_n, "L4", extra=ddrsettings)
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add_vec(ddrphy0.sd_a, ["B1", "B2", "H8", "J7", "E4", "D5", "K7", "F5",
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"G6", "C1", "C3", "D1", "D2"], extra=ddrsettings)
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add_vec(ddrphy0.sd_ba, ["A2", "E6"], extra=ddrsettings)
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add(ddrphy0.sd_cs_n, "F7", extra=ddrsettings)
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add(ddrphy0.sd_cke, "G7", extra=ddrsettings)
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add(ddrphy0.sd_ras_n, "E5", extra=ddrsettings)
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add(ddrphy0.sd_cas_n, "C4", extra=ddrsettings)
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add(ddrphy0.sd_we_n, "D3", extra=ddrsettings)
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add_vec(ddrphy0.sd_dq, ["Y2", "W3", "W1", "P8", "P7", "P6", "P5", "T4", "T3",
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"U4", "V3", "N6", "N7", "M7", "M8", "R4", "P4", "M6", "L6", "P3", "N4",
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"M5", "V2", "V1", "U3", "U1", "T2", "T1", "R3", "R1", "P2", "P1"],
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extra=ddrsettings)
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add_vec(ddrphy0.sd_dm, ["E1", "E3", "F3", "G4"], extra=ddrsettings)
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add_vec(ddrphy0.sd_dqs, ["F1", "F2", "H5", "H6"], extra=ddrsettings)
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2012-05-19 18:30:03 -04:00
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add(minimac0.phy_rst_n, "R22")
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add(minimac0.phy_dv, "V21")
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add(minimac0.phy_rx_clk, "H22")
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add(minimac0.phy_rx_er, "V22")
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add_vec(minimac0.phy_rx_data, ["U22", "U20", "T22", "T21"])
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add(minimac0.phy_tx_en, "N19")
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add(minimac0.phy_tx_clk, "H21")
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add(minimac0.phy_tx_er, "M19")
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add_vec(minimac0.phy_tx_data, ["M16", "L15", "P19", "P20"])
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add(minimac0.phy_col, "W20")
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add(minimac0.phy_crs, "W22")
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2012-06-17 07:41:26 -04:00
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add_vec(fb0.vga_r, ["C6", "B6", "A6", "C7", "A7", "B8", "A8", "D9"])
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add_vec(fb0.vga_g, ["C8", "C9", "A9", "D7", "D8", "D10", "C10", "B10"])
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add_vec(fb0.vga_b, ["D11", "C12", "B12", "A12", "C13", "A13", "D14", "C14"])
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add(fb0.vga_hsync_n, "A14")
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add(fb0.vga_vsync_n, "C15")
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add(fb0.vga_psave_n, "B14")
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2012-05-19 18:30:03 -04:00
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self._phy_rx_clk = minimac0.phy_rx_clk
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self._phy_tx_clk = minimac0.phy_tx_clk
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2012-04-02 13:22:17 -04:00
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def get_ios(self):
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return set([c[0] for c in self.constraints])
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def get_ucf(self, ns):
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r = ""
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for c in self.constraints:
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r += "NET \"" + ns.get_name(c[0])
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if c[1] >= 0:
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r += "(" + str(c[1]) + ")"
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r += "\" LOC = " + c[2]
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r += " | IOSTANDARD = " + c[3]
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if c[4]:
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r += " | " + c[4]
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r += ";\n"
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r += """
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2011-12-13 11:33:12 -05:00
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TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
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2012-02-19 12:43:42 -05:00
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INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
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INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
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2012-02-19 14:49:56 -05:00
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PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
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2012-05-19 18:30:03 -04:00
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NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk";
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NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk";
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TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;
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TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%;
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TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
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TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
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2012-07-01 12:14:16 -04:00
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NET "asfifo*/counter_read/gray_count*" TIG;
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NET "asfifo*/counter_write/gray_count*" TIG;
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NET "asfifo*/preset_empty*" TIG;
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2012-05-19 18:30:03 -04:00
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""".format(phy_rx_clk=ns.get_name(self._phy_rx_clk), phy_tx_clk=ns.get_name(self._phy_tx_clk))
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2011-12-13 11:33:12 -05:00
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2012-04-02 13:22:17 -04:00
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return r
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