litex/README

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                         Migen inside

                Build your hardware, easily!
              Copyright 2012-2018 / EnjoyDigital

[> Intro
--------
LiteX is an alternative to MiSoC maintained and used by Enjoy-Digital to build
our cores, integrate them in complete SoC and load/flash them to the hardware
and experiment new features. (structure is kept close to MiSoC to ease
collaboration)

Typical LiteX design flow:
--------------------------

                        +---------------+
                        |FPGA toolchains|
                        +----^-----+----+
                             |     |
                          +--+-----v--+
         +-------+        |           |
         | Migen +-------->           |
         +-------+        |           |        Your design
                          |   LiteX   +---> ready to be used!
                          |           |
+----------------------+  |           |
|LiteX Cores Ecosystem +-->           |
+----------------------+  +-^-------^-+
 (Eth, SATA, DRAM, USB,     |       |
  PCIe, Video, etc...)      +       +
                           board   target
                           file    file


[> Sub-packages
---------------
gen:
  Provides specific or experimental modules to generate HDL that are not integrated
  in Migen.

build:
  Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
  simulate HDL code or full SoCs.

soc:
  Provides definitions/modules to build cores (bus, bank, flow), cores and tools
  to build a SoC from such cores.

boards:
  Provides platforms and targets for the supported boards.

[> Very Quick start guide (for newcomers)
-----------------------------------------
TimVideos.us has done an awesome job for setting up a LiteX environment easily in
the litex-buildenv repo: https://github.com/timvideos/litex-buildenv

It's recommended for newcomers to go this way. Various FPGA boards are supported
and multiple examples provided! You can even run Linux on your FPGA using LiteX
very easily!

Migen documentation can be found here: https://m-labs.hk/migen/manual


[> Quick start guide (for advanced users)
-----------------------------------------
0. If cloned from Git without the --recursive option, get the submodules:
  git submodule update --init

1. Install Python 3.5, Migen and FPGA vendor's development tools.
   Get Migen from: https://github.com/m-labs/migen

2. Compile and install binutils. Take the latest version from GNU.
  mkdir build && cd build
  ../configure --target=lm32-elf
  make
  make install

3. (Optional, only if you want to use a lm32 CPU in you SoC)
  Compile and install GCC. Take gcc-core and gcc-g++ from GNU
  (version 4.5 or >=4.9).
  rm -rf libstdc++-v3
  mkdir build && cd build
  ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \
    --disable-libssp
  make
  make install

4. Build the target of your board...:
  Go to boards/targets and execute the target you want to build

5. ... and/or install Verilator and test LiteX on your computer:
  Download and install Verilator: http://www.veripool.org/
  Install libevent-devel / json-c-devel packages
  Go to boards/targets
  ./sim.py

6. Run a terminal program on the board's serial port at 115200 8-N-1.
  You should get the BIOS prompt.

[> Contact
----------
E-mail: florent [AT] enjoy-digital.fr