2015-02-21 17:13:43 -05:00
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.bank.eventmanager import *
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from migen.genlib.fifo import SyncFIFOBuffered
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2015-03-22 05:56:29 -04:00
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from misoclib.com.liteusb.common import *
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2015-02-21 17:13:43 -05:00
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class FtdiUART(Module, AutoCSR):
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def __init__(self, tag, fifo_depth=64):
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self.tag = tag
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self._rxtx = CSR(8)
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self.submodules.ev = EventManager()
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self.ev.tx = EventSourcePulse()
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self.ev.rx = EventSourceLevel()
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self.ev.finalize()
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self.source = source = Source(user_layout)
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self.sink = sink = Sink(user_layout)
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###
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# TX
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tx_start = self._rxtx.re
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tx_done = self.ev.tx.trigger
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self.sync += \
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If(tx_start,
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source.stb.eq(1),
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source.d.eq(self._rxtx.r),
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).Elif(tx_done,
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source.stb.eq(0)
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)
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self.comb += [
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source.sop.eq(1),
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source.eop.eq(1),
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source.length.eq(1),
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source.dst.eq(self.tag),
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tx_done.eq(source.stb & source.ack),
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]
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# RX
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rx_available = self.ev.rx.trigger
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rx_fifo = SyncFIFOBuffered(8, fifo_depth)
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self.submodules += rx_fifo
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self.comb += [
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rx_fifo.we.eq(sink.stb),
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sink.ack.eq(sink.stb & rx_fifo.writable),
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rx_fifo.din.eq(sink.d),
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rx_available.eq(rx_fifo.readable),
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rx_fifo.re.eq(self.ev.rx.clear),
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self._rxtx.w.eq(rx_fifo.dout)
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]
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