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| __|___ |_|___ _ _ | \|_|___|_| |_ ___| |
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| __| | | | . | | | | | | | . | | _| .'| |
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|_____|_|_|_| |___|_ | |____/|_|_ |_|_| |__,|_|
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Copyright 2012 / Florent Kermarrec / florent@enjoy-digital.fr
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2013-02-22 08:28:05 -05:00
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miscope
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2013-02-22 08:28:05 -05:00
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[> miscope
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2012-08-12 08:38:49 -04:00
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------------
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2013-02-22 08:28:05 -05:00
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miscope is a small logic analyzer to be embedded in an FPGA.
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While free vendor toolchains are generally used by beginners or for prototyping
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(situations where having a logic analyser in the design is generally very
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2013-02-27 18:32:42 -05:00
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helpful) free toolchains are always provided without the proprietary logic
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analyzer solution... :(
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Based on Migen, miscope aims to provide a free, portable and flexible
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alternative to vendor's solutions!
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[> Specification:
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2013-02-22 08:28:05 -05:00
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miscope provides Migen cores to be embedded in the design and Python drivers to
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control the logic analyzer from the Host. miscope automatically interconnects
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all cores to the CSR bus. When using Python on the Host, no needs to worry about
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cores register mapping, importing miscope project gives you direct access to
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2013-01-21 16:40:36 -05:00
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all the cores!
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2013-02-27 18:32:42 -05:00
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miscope produces .vcd output files to be analyzed in your favorite waveform viewer.
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2012-08-12 08:38:49 -04:00
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[> Status:
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2013-02-26 17:41:22 -05:00
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Refactoring in progress...
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2013-01-21 16:40:36 -05:00
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[> Examples:
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test_MigIo : Led & Switch Test controlled by Python Host.
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test_MigLa : Logic Analyzer controlled by Python Host.
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2012-09-09 17:46:26 -04:00
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2012-08-12 08:38:49 -04:00
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[> Contact
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E-mail: florent@enjoy-digital.fr
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