2015-01-28 03:14:01 -05:00
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from collections import OrderedDict
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from migen.fhdl.std import *
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2015-01-27 18:33:26 -05:00
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from migen.fhdl.std import *
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2015-01-28 03:14:01 -05:00
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from migen.genlib.resetsync import AsyncResetSynchronizer
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2015-01-28 05:45:19 -05:00
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from migen.genlib.record import *
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from migen.genlib.fsm import FSM, NextState
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2015-01-28 13:07:59 -05:00
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from migen.genlib.misc import chooser
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2015-01-27 18:33:26 -05:00
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from migen.flow.actor import EndpointDescription
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2015-01-28 05:45:19 -05:00
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from migen.flow.actor import Sink, Source
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from migen.actorlib.structuring import Converter, Pipeline
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from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
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from migen.bank.description import *
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2015-01-27 18:33:26 -05:00
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eth_mtu = 1532
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eth_preamble = 0xD555555555555555
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buffer_depth = 2**log2_int(eth_mtu, need_pow2=False)
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2015-01-28 05:45:19 -05:00
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def eth_phy_description(dw):
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layout = [
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("data", dw),
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("error", dw//8)
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]
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return EndpointDescription(layout, packetized=True)
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def eth_mac_description(dw):
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2015-01-27 18:33:26 -05:00
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layout = [
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2015-01-28 05:45:19 -05:00
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("data", dw),
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2015-01-27 18:33:26 -05:00
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("last_be", dw//8),
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("error", dw//8)
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]
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return EndpointDescription(layout, packetized=True)
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