2015-05-01 14:20:20 -04:00
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from migen.fhdl.std import *
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from misoclib.com.liteusb.common import *
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2015-05-09 09:48:54 -04:00
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from misoclib.tools.wishbone import WishboneStreamingBridge
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2015-05-01 14:20:20 -04:00
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2015-05-09 09:48:54 -04:00
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class LiteUSBWishboneBridge(WishboneStreamingBridge):
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2015-05-01 14:20:20 -04:00
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def __init__(self, port, clk_freq):
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2015-05-09 09:48:54 -04:00
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WishboneStreamingBridge.__init__(self, port, clk_freq)
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2015-05-02 10:15:58 -04:00
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self.comb += port.sink.dst.eq(port.tag)
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