2012-01-31 15:46:08 -05:00
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#!/usr/bin/env python3
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2011-12-24 07:46:08 -05:00
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2015-04-13 14:54:19 -04:00
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import sys
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2012-03-10 14:01:14 -05:00
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from setuptools import setup
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from setuptools import find_packages
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2011-12-24 07:46:08 -05:00
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2018-02-22 05:52:10 -05:00
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if sys.version_info[:3] < (3, 5):
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raise SystemExit("You need Python 3.5+")
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2015-09-24 04:08:39 -04:00
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2011-12-24 07:46:08 -05:00
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setup(
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2015-11-07 06:26:46 -05:00
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name="litex",
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2018-02-23 07:36:32 -05:00
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version="0.2.dev",
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2015-11-07 06:26:46 -05:00
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description="Python tools to design FPGA cores and SoCs",
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long_description=open("README").read(),
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author="Florent Kermarrec",
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author_email="florent@enjoy-digital.fr",
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url="http://enjoy-digital.fr",
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download_url="https://github.com/enjoy-digital/litex",
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2017-04-24 12:45:02 -04:00
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test_suite="test",
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2015-04-13 14:07:07 -04:00
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license="BSD",
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platforms=["Any"],
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keywords="HDL ASIC FPGA hardware design",
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classifiers=[
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"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
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"Environment :: Console",
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2018-02-22 05:52:10 -05:00
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"Development Status :: Alpha",
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"Intended Audience :: Developers",
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"License :: OSI Approved :: BSD License",
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"Operating System :: OS Independent",
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"Programming Language :: Python",
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],
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2018-07-19 05:35:50 -04:00
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packages=find_packages(exclude=("test*", "sim*", "doc*")),
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2018-01-11 01:43:16 -05:00
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install_requires=["pyserial"],
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2015-11-07 06:26:46 -05:00
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include_package_data=True,
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entry_points={
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"console_scripts": [
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2019-04-20 04:44:53 -04:00
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"litex_term=litex.tools.litex_term:main",
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"litex_server=litex.tools.litex_server:main",
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"litex_sim=litex.tools.litex_sim:main",
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"litex_read_verilog=litex.tools.litex_read_verilog:main",
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2018-09-23 19:24:51 -04:00
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"litex_simple=litex.boards.targets.simple:main",
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2015-11-07 06:26:46 -05:00
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],
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},
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2011-12-24 07:46:08 -05:00
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)
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