2013-01-27 07:59:44 -05:00
|
|
|
_____ _ ____ _ _ _ _
|
2013-01-21 16:40:36 -05:00
|
|
|
| __|___ |_|___ _ _ | \|_|___|_| |_ ___| |
|
|
|
|
|
| __| | | | . | | | | | | | . | | _| .'| |
|
|
|
|
|
|_____|_|_|_| |___|_ | |____/|_|_ |_|_| |__,|_|
|
|
|
|
|
|___| |___| |___|
|
|
|
|
|
|
2014-04-20 18:31:02 -04:00
|
|
|
Copyright 2012-2014 / Florent Kermarrec / florent@enjoy-digital.fr
|
2013-01-21 16:40:36 -05:00
|
|
|
|
2013-03-21 07:23:44 -04:00
|
|
|
Miscope
|
2013-01-21 16:40:36 -05:00
|
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
2013-03-21 07:23:44 -04:00
|
|
|
[> Miscope
|
2012-08-12 08:38:49 -04:00
|
|
|
------------
|
|
|
|
|
|
2013-03-21 07:23:44 -04:00
|
|
|
Miscope is a small logic analyzer to embed in an FPGA.
|
2013-01-21 16:40:36 -05:00
|
|
|
|
|
|
|
|
While free vendor toolchains are generally used by beginners or for prototyping
|
2014-08-03 02:38:37 -04:00
|
|
|
(situations where having a logic analyzer in the design is generally helpful)
|
2013-03-21 07:23:44 -04:00
|
|
|
free toolchains are always provided without the proprietary logic analyzer
|
|
|
|
|
solution... :(
|
2013-01-21 16:40:36 -05:00
|
|
|
|
2014-08-03 02:38:37 -04:00
|
|
|
Baseid on Migen, Miscope aims to provide a free, portable and flexible
|
|
|
|
|
alternatve to vendor's solutions!
|
2013-01-21 16:40:36 -05:00
|
|
|
|
|
|
|
|
[> Specification:
|
|
|
|
|
|
2013-03-21 07:23:44 -04:00
|
|
|
Miscope provides Migen cores to embed in the design and Python drivers to control
|
|
|
|
|
the logic analyzer from the Host. Miscope automatically interconnects all cores
|
2014-08-03 02:38:37 -04:00
|
|
|
to a CSR bus. When using Python on the Host, no needs to worry about cores register
|
2013-03-21 07:23:44 -04:00
|
|
|
mapping, importing miscope project gives you direct access to all the cores!
|
2013-01-21 16:40:36 -05:00
|
|
|
|
2013-03-21 07:23:44 -04:00
|
|
|
Miscope produces .vcd output files to be analyzed in your favorite waveform viewer.
|
|
|
|
|
|
2014-04-20 18:31:02 -04:00
|
|
|
Since Miscope also provides an Uart2Wishbone bridge, you only need 2 external Rx/Tx
|
|
|
|
|
pins to be ready to debug!
|
2013-04-15 10:26:49 -04:00
|
|
|
|
2012-08-12 08:38:49 -04:00
|
|
|
[> Status:
|
2014-08-03 02:38:37 -04:00
|
|
|
MiIo & Mila working on board with standard term.
|
2013-03-23 08:57:59 -04:00
|
|
|
RLE working on board.
|
2013-03-21 07:23:44 -04:00
|
|
|
RangeDetector and EdgeDector terms not tested.
|
2013-01-21 16:40:36 -05:00
|
|
|
|
|
|
|
|
[> Examples:
|
2014-04-20 18:31:02 -04:00
|
|
|
Have a look at http://github.com/Florent-Kermarrec/misoc-de0nano
|
2014-08-03 11:01:58 -04:00
|
|
|
test_miio.py : Led & Switch Test controlled by Python Host.
|
|
|
|
|
test_mila.py : Logic Analyzer controlled by Python Host.
|
2012-09-09 17:46:26 -04:00
|
|
|
|
2012-08-12 08:38:49 -04:00
|
|
|
[> Contact
|
|
|
|
|
E-mail: florent@enjoy-digital.fr
|
