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targets/ulx3s: revert to cl=2

This commit is contained in:
Florent Kermarrec 2019-09-25 14:09:44 +02:00
parent a9d55b04c0
commit 015b65fe88
1 changed files with 1 additions and 1 deletions
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2
litex/boards/targets/ulx3s.py
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@ -63,7 +63,7 @@ class BaseSoC(SoCSDRAM):
self.submodules.crg = _CRG(platform, sys_clk_freq)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=3)
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2)
sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,