Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

litesata/example_designs: fix core generation (RAID introduced some changes on the PHY)

This commit is contained in:
Florent Kermarrec 2015-06-26 00:20:58 +02:00
parent c615b50735
commit 04c64eb1d8
3 changed files with 14 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
misoclib/mem/litesata/example_designs/platforms/verilog_backend.py
View File

@ -4,14 +4,15 @@ from mibuild.xilinx.platform import XilinxPlatform
_io = [ _io = [
("sys_clk", 0, Pins("X")), ("sys_clk", 0, Pins("X")),
("sys_rst", 1, Pins("X")), ("sys_rst", 1, Pins("X")),
("sata_clocks", 0,
Subsignal("refclk_p", Pins("X")),
Subsignal("refclk_n", Pins("X")),
),
("sata", 0, ("sata", 0,
Subsignal("refclk_p", Pins("C8")), Subsignal("txp", Pins("X")),
Subsignal("refclk_n", Pins("C7")), Subsignal("txn", Pins("X")),
Subsignal("txp", Pins("D2")), Subsignal("rxp", Pins("X")),
Subsignal("txn", Pins("D1")), Subsignal("rxn", Pins("X")),
Subsignal("rxp", Pins("E4")),
Subsignal("rxn", Pins("E3")),
), ),
] ]

6
misoclib/mem/litesata/example_designs/targets/core.py
View File

@ -17,7 +17,7 @@ class Core(Module):
self.clk_freq = clk_freq self.clk_freq = clk_freq
# SATA PHY/Core/Frontend # SATA PHY/Core/Frontend
self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sys_clk"), platform.request("sata"), "sata_gen2", clk_freq) self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata"), "sata_gen2", clk_freq)
self.submodules.sata_core = LiteSATACore(self.sata_phy) self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core) self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
@ -32,6 +32,10 @@ class Core(Module):
ios = set() ios = set()
# Transceiver # Transceiver
for e in dir(self.sata_phy.clock_pads):
obj = getattr(self.sata_phy.clock_pads, e)
if isinstance(obj, Signal):
ios = ios.union({obj})
for e in dir(self.sata_phy.pads): for e in dir(self.sata_phy.pads):
obj = getattr(self.sata_phy.pads, e) obj = getattr(self.sata_phy.pads, e)
if isinstance(obj, Signal): if isinstance(obj, Signal):

1
misoclib/mem/litesata/phy/__init__.py
View File

@ -5,6 +5,7 @@ from misoclib.mem.litesata.phy.datapath import *
class LiteSATAPHY(Module): class LiteSATAPHY(Module):
def __init__(self, device, clock_pads_or_refclk, pads, revision, clk_freq): def __init__(self, device, clock_pads_or_refclk, pads, revision, clk_freq):
self.clock_pads = clock_pads_or_refclk
self.pads = pads self.pads = pads
self.revision = revision self.revision = revision