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cpu/naxriscv/vexriscv_smp: Declare/Add OpenSBI region in add_soc_compoents.

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Avoid doing it in Linux-on-LiteX-Vexriscv.
This commit is contained in:
Florent Kermarrec 2022-03-17 16:28:25 +01:00
parent b4db2a3ef2
commit 05724d9fea
2 changed files with 6 additions and 0 deletions
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3
litex/soc/cores/cpu/naxriscv/core.py
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@ -261,6 +261,9 @@ class NaxRiscv(CPU):
soc.irq.add("uart", n=0)
soc.irq.add("timer0", n=1)
# Add OpenSBI region.
soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f00000, 0x80000, type="cached+linker")
# Define ISA.
soc.add_constant("CPU_ISA", NaxRiscv.get_arch())

3
litex/soc/cores/cpu/vexriscv_smp/core.py
View file

@ -382,6 +382,9 @@ class VexRiscvSMP(CPU):
soc.irq.add("uart", n=0)
soc.irq.add("timer0", n=1)
# Add OpenSBI region.
soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f00000, 0x80000, type="cached+linker")
# Define number of CPUs
soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count)
soc.add_constant("CPU_ISA", VexRiscvSMP.get_arch())