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interconnect/csr, wishbone: use reset_less on datapath signals.

This commit is contained in:
Florent Kermarrec 2020-04-06 13:11:50 +02:00
parent b95965de73
commit 05b1b7787b
2 changed files with 15 additions and 8 deletions
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7
litex/soc/interconnect/csr_bus.py
View File

@ -39,6 +39,9 @@ class Interface(Record):
Record.__init__(self, set_layout_parameters(_layout, Record.__init__(self, set_layout_parameters(_layout,
data_width = data_width, data_width = data_width,
address_width = address_width)) address_width = address_width))
self.adr.reset_less = True
self.dat_w.reset_less = True
self.dat_r.reset_less = True
@classmethod @classmethod
def like(self, other): def like(self, other):
@ -120,7 +123,7 @@ class SRAM(Module):
adr_shift = log2_int(bus.alignment//32) adr_shift = log2_int(bus.alignment//32)
if word_bits: if word_bits:
word_index = Signal(word_bits) word_index = Signal(word_bits, reset_less=True)
word_expanded = Signal(csrw_per_memw*data_width) word_expanded = Signal(csrw_per_memw*data_width)
self.sync += word_index.eq(self.bus.adr[adr_shift:adr_shift+word_bits]) self.sync += word_index.eq(self.bus.adr[adr_shift:adr_shift+word_bits])
self.comb += [ self.comb += [
@ -132,7 +135,7 @@ class SRAM(Module):
if not read_only: if not read_only:
wregs = [] wregs = []
for i in range(csrw_per_memw-1): for i in range(csrw_per_memw-1):
wreg = Signal(data_width) wreg = Signal(data_width, reset_less=True)
self.sync += If(sel & self.bus.we & (self.bus.adr[adr_shift:adr_shift+word_bits] == i), wreg.eq(self.bus.dat_w)) self.sync += If(sel & self.bus.we & (self.bus.adr[adr_shift:adr_shift+word_bits] == i), wreg.eq(self.bus.dat_w))
wregs.append(wreg) wregs.append(wreg)
memword_chunks = [self.bus.dat_w] + list(reversed(wregs)) memword_chunks = [self.bus.dat_w] + list(reversed(wregs))

16
litex/soc/interconnect/wishbone.py
View File

@ -38,9 +38,13 @@ class Interface(Record):
self.data_width = data_width self.data_width = data_width
self.adr_width = adr_width self.adr_width = adr_width
Record.__init__(self, set_layout_parameters(_layout, Record.__init__(self, set_layout_parameters(_layout,
adr_width=adr_width, adr_width = adr_width,
data_width=data_width, data_width = data_width,
sel_width=data_width//8)) sel_width = data_width//8))
self.adr.reset_less = True
self.dat_w.reset_less = True
self.dat_r.reset_less = True
self.sel.reset_less = True
@staticmethod @staticmethod
def like(other): def like(other):
@ -311,7 +315,7 @@ class DownConverter(Module):
self.comb += Case(counter, cases) self.comb += Case(counter, cases)
cached_data = Signal(dw_from) cached_data = Signal(dw_from, reset_less=True)
self.comb += master.dat_r.eq(Cat(cached_data[dw_to:], slave.dat_r)) self.comb += master.dat_r.eq(Cat(cached_data[dw_to:], slave.dat_r))
self.sync += \ self.sync += \
If(read & counter_ce, If(read & counter_ce,
@ -553,7 +557,7 @@ class Cache(Module):
if adr_offset is None: if adr_offset is None:
adr_offset_r = None adr_offset_r = None
else: else:
adr_offset_r = Signal(offsetbits) adr_offset_r = Signal(offsetbits, reset_less=True)
self.sync += adr_offset_r.eq(adr_offset) self.sync += adr_offset_r.eq(adr_offset)
self.comb += [ self.comb += [
@ -707,7 +711,7 @@ class SRAM(Module):
# generate ack # generate ack
self.sync += [ self.sync += [
self.bus.ack.eq(0), self.bus.ack.eq(0),
If(self.bus.cyc & self.bus.stb & ~self.bus.ack, self.bus.ack.eq(1)) If(self.bus.cyc & self.bus.stb & ~self.bus.ack, self.bus.ack.eq(1))
] ]