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cpu: Specify clock domain (improve readability).

This commit is contained in:
Florent Kermarrec 2021-05-17 10:51:54 +02:00
parent 78bdde0424
commit 06f4658174
9 changed files with 28 additions and 28 deletions
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4
litex/soc/cores/cpu/blackparrot/core.py
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@ -92,8 +92,8 @@ class BlackParrotRV64(CPU):
self.cpu_params = dict( self.cpu_params = dict(
# Clk / Rst. # Clk / Rst.
i_clk_i = ClockSignal(), i_clk_i = ClockSignal("sys"),
i_reset_i = ResetSignal() | self.reset, i_reset_i = ResetSignal("sys") | self.reset,
# Wishbone (I/D). # Wishbone (I/D).
i_wbm_dat_i = idbus.dat_r, i_wbm_dat_i = idbus.dat_r,

12
litex/soc/cores/cpu/cv32e40p/core.py
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@ -240,8 +240,8 @@ class TraceDebugger(Module):
self.trace_params = dict( self.trace_params = dict(
# Clk / Rst. # Clk / Rst.
i_clk_i = ClockSignal(), i_clk_i = ClockSignal("sys"),
i_rst_ni = ~ResetSignal(), i_rst_ni = ~ResetSignal("sys"),
i_test_mode_i = 0, i_test_mode_i = 0,
# CPU Interface. # CPU Interface.
@ -309,8 +309,8 @@ class DebugModule(Module):
self.dm_params = dict( self.dm_params = dict(
# Clk / Rst. # Clk / Rst.
i_clk = ClockSignal(), i_clk = ClockSignal("sys"),
i_rst_n = ~ResetSignal(), i_rst_n = ~ResetSignal("sys"),
o_ndmreset = self.ndmreset, o_ndmreset = self.ndmreset,
o_debug_req = self.debug_req, o_debug_req = self.debug_req,
@ -398,8 +398,8 @@ class CV32E40P(CPU):
self.cpu_params = dict( self.cpu_params = dict(
# Clk / Rst. # Clk / Rst.
i_clk_i = ClockSignal(), i_clk_i = ClockSignal("sys"),
i_rst_ni = ~ResetSignal(), i_rst_ni = ~ResetSignal("sys"),
# Controls. # Controls.
i_clock_en_i = 1, i_clock_en_i = 1,

4
litex/soc/cores/cpu/ibex/core.py
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@ -143,8 +143,8 @@ class Ibex(CPU):
i_hart_id_i = 0, i_hart_id_i = 0,
# Clk/Rst. # Clk/Rst.
i_clk_i = ClockSignal(), i_clk_i = ClockSignal("sys"),
i_rst_ni = ~ResetSignal(), i_rst_ni = ~ResetSignal("sys"),
# Instruction bus. # Instruction bus.
o_instr_req_o = ibus.req, o_instr_req_o = ibus.req,

12
litex/soc/cores/cpu/microwatt/core.py
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@ -78,8 +78,8 @@ class Microwatt(CPU):
self.cpu_params = dict( self.cpu_params = dict(
# Clk / Rst. # Clk / Rst.
i_clk = ClockSignal(), i_clk = ClockSignal("sys"),
i_rst = ResetSignal() | self.reset, i_rst = ResetSignal("sys") | self.reset,
# IBus. # IBus.
i_wishbone_insn_dat_r = ibus.dat_r, i_wishbone_insn_dat_r = ibus.dat_r,
@ -235,8 +235,8 @@ class XICSSlave(Module, AutoCSR):
self.icp_params = dict( self.icp_params = dict(
# Clk / Rst. # Clk / Rst.
i_clk = ClockSignal(), i_clk = ClockSignal("sys"),
i_rst = ResetSignal(), i_rst = ResetSignal("sys"),
# Wishbone Bus. # Wishbone Bus.
o_wishbone_dat_r = icp_bus.dat_r, o_wishbone_dat_r = icp_bus.dat_r,
@ -257,8 +257,8 @@ class XICSSlave(Module, AutoCSR):
self.ics_params = dict( self.ics_params = dict(
# Clk / Rst. # Clk / Rst.
i_clk = ClockSignal(), i_clk = ClockSignal("sys"),
i_rst = ResetSignal(), i_rst = ResetSignal("sys"),
# Wishbone Bus. # Wishbone Bus.
o_wishbone_dat_r = ics_bus.dat_r, o_wishbone_dat_r = ics_bus.dat_r,

4
litex/soc/cores/cpu/minerva/core.py
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@ -53,8 +53,8 @@ class Minerva(CPU):
self.cpu_params = dict( self.cpu_params = dict(
# Clk / Rst. # Clk / Rst.
i_clk = ClockSignal(), i_clk = ClockSignal("sys"),
i_rst = ResetSignal() | self.reset, i_rst = ResetSignal("sys") | self.reset,
# IRQ. # IRQ.
i_timer_interrupt = 0, i_timer_interrupt = 0,

4
litex/soc/cores/cpu/mor1kx/core.py
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@ -154,8 +154,8 @@ class MOR1KX(CPU):
**cpu_args, **cpu_args,
# Clk / Rst. # Clk / Rst.
i_clk = ClockSignal(), i_clk = ClockSignal("sys"),
i_rst = ResetSignal() | self.reset, i_rst = ResetSignal("sys") | self.reset,
# IRQ. # IRQ.
i_irq_i=self.interrupt, i_irq_i=self.interrupt,

4
litex/soc/cores/cpu/picorv32/core.py
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@ -123,8 +123,8 @@ class PicoRV32(CPU):
self.cpu_params.update( self.cpu_params.update(
# Clk / Rst. # Clk / Rst.
i_clk = ClockSignal(), i_clk = ClockSignal("sys"),
i_resetn = ~(ResetSignal() | self.reset), i_resetn = ~(ResetSignal("sys") | self.reset),
# Trap. # Trap.
o_trap = self.trap, o_trap = self.trap,

4
litex/soc/cores/cpu/rocket/core.py
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@ -128,8 +128,8 @@ class RocketRV64(CPU):
self.cpu_params = dict( self.cpu_params = dict(
# Clk / Rst. # Clk / Rst.
i_clock = ClockSignal(), i_clock = ClockSignal("sys"),
i_reset = ResetSignal() | self.reset, i_reset = ResetSignal("sys") | self.reset,
# Debug (ignored). # Debug (ignored).
i_resetctrl_hartIsInReset_0 = Open(), i_resetctrl_hartIsInReset_0 = Open(),

8
litex/soc/cores/cpu/vexriscv/core.py
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@ -136,8 +136,8 @@ class VexRiscv(CPU, AutoCSR):
# # # # # #
self.cpu_params = dict( self.cpu_params = dict(
i_clk = ClockSignal(), i_clk = ClockSignal("sys"),
i_reset = ResetSignal() | self.reset, i_reset = ResetSignal("sys") | self.reset,
i_externalInterruptArray = self.interrupt, i_externalInterruptArray = self.interrupt,
i_timerInterrupt = 0, i_timerInterrupt = 0,
@ -310,8 +310,8 @@ class VexRiscv(CPU, AutoCSR):
i_rsp_ready = cfu_bus.rsp.ready, i_rsp_ready = cfu_bus.rsp.ready,
o_rsp_payload_response_ok = cfu_bus.rsp.payload.response_ok, o_rsp_payload_response_ok = cfu_bus.rsp.payload.response_ok,
o_rsp_payload_outputs_0 = cfu_bus.rsp.payload.outputs_0, o_rsp_payload_outputs_0 = cfu_bus.rsp.payload.outputs_0,
i_clk = ClockSignal(), i_clk = ClockSignal("sys"),
i_reset = ResetSignal(), i_reset = ResetSignal("sys"),
) )
self.platform.add_source(cfu_filename) self.platform.add_source(cfu_filename)