Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

build/DDRTristate: Fix inconsistencies with SDRTristate (o/i swap).

Browse source
This commit is contained in:
Florent Kermarrec 2021-09-21 08:18:03 +02:00
parent 1e24fd87d1
commit 08779202f4
3 changed files with 18 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

26
litex/build/io.py
View file

@ -148,40 +148,40 @@ class DDROutput(Special):
# DDR Tristate -------------------------------------------------------------------------------------
class InferedDDRTristate(Module):
def __init__(self, i1, i2, o1, o2, oe1, oe2, io, clk):
def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk):
_o = Signal()
_oe = Signal()
_i = Signal()
self.specials += DDROutput(i1, i2, _o, clk)
self.specials += DDROutput(o1, o2, _o, clk)
self.specials += DDROutput(oe1, oe2, _oe, clk)
self.specials += DDRInput(_i, o1, o2, clk)
self.specials += DDRInput(_i, i1, i2, clk)
self.specials += Tristate(io, _o, _oe, _i)
class DDRTristate(Special):
def __init__(self, i1, i2, o1, o2, oe1, oe2, io, clk=ClockSignal()):
def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk=ClockSignal()):
Special.__init__(self)
self.i1 = i1
self.i2 = i2
self.io = io
self.o1 = o1
self.o2 = o2
self.oe1 = oe1
self.oe2 = oe2
self.io = io
self.i1 = i1
self.i2 = i2
self.clk = clk
def iter_expressions(self):
yield self, "io", SPECIAL_INOUT
yield self, "i1", SPECIAL_INPUT
yield self, "i2", SPECIAL_INPUT
yield self, "o1", SPECIAL_OUTPUT
yield self, "o2", SPECIAL_OUTPUT
yield self, "io", SPECIAL_INOUT
yield self, "o1", SPECIAL_INPUT
yield self, "o2", SPECIAL_INPUT
yield self, "oe1", SPECIAL_INPUT
yield self, "oe2", SPECIAL_INPUT
yield self, "i1", SPECIAL_OUTPUT
yield self, "i2", SPECIAL_OUTPUT
yield self, "clk", SPECIAL_INPUT
@staticmethod
def lower(dr):
return InferedDDRTristate(dr.i1, dr.i2, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.io, dr.clk)
return InferedDDRTristate(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk)
# Clock Reset Generator ----------------------------------------------------------------------------

6
litex/build/lattice/common.py
View file

@ -305,9 +305,9 @@ class LatticeNXDDRTristateImpl(Module):
_o = Signal()
_oe = Signal()
_i = Signal()
self.specials += DDROutput(i1, i2, _o, clk)
self.specials += SDROutput(oe1|oe2, _oe, clk)
self.specials += DDRInput(_i, o1, o2, clk)
self.specials += DDROutput(o1, o2, _o, clk)
self.specials += SDROutput(oe1 | oe2, _oe, clk)
self.specials += DDRInput(_i, i1, i2, clk)
self.specials += Tristate(io, _o, _oe, _i)
_oe.attr.add("syn_useioff")

4
litex/build/xilinx/common.py
View file

@ -159,9 +159,9 @@ class XilinxDDRTristateImpl(Module):
_o = Signal()
_oe_n = Signal()
_i = Signal()
self.specials += DDROutput(i1, i2, _o, clk)
self.specials += DDROutput(o1, o2, _o, clk)
self.specials += DDROutput(~oe1, ~oe2, _oe_n, clk)
self.specials += DDRInput(_i, o1, o2, clk)
self.specials += DDRInput(_i, i1, i2, clk)
self.specials += Instance("IOBUF",
io_IO = io,
o_O = _i,