litex/gen: Split common in common/context/reduce/signal.
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@ -1,3 +1,8 @@
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from litex.gen.sim import *
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from litex.gen.sim import *
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from litex.gen.common import *
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from litex.gen.common import *
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from litex.gen.signal import *
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from litex.gen.reduce import *
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from litex.gen.context import *
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from litex.gen.fhdl.module import *
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from litex.gen.fhdl.module import *
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@ -24,58 +24,7 @@ def colorer(s, color="bright"):
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def reverse_bits(s):
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def reverse_bits(s):
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return s[::-1]
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return s[::-1]
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def reverse_bytes(s):
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def reverse_bytes(s):
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n = (len(s) + 7)//8
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n = (len(s) + 7)//8
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return Cat(*[s[i*8:min((i + 1)*8, len(s))]
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return Cat(*[s[i*8:min((i + 1)*8, len(s))]
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for i in reversed(range(n))])
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for i in reversed(range(n))])
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# Context ------------------------------------------------------------------------------------------
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# FIXME: PoC to fix Efinix AsyncFIFO issue, think a bit more about it to see how to do it properly.
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class LiteXContext:
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platform = None
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toolchain = None
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device = None
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soc = None
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# Signals ------------------------------------------------------------------------------------------
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class Open(Signal): pass
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class Unsigned(Signal):
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def __init__(self, bits=1, *args, **kwargs):
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assert isinstance(bits, int)
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Signal.__init__(self, bits_sign=(bits, 0), *args, **kwargs)
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class Signed(Signal):
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def __init__(self, bits=1, *args, **kwargs):
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assert isinstance(bits, int)
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Signal.__init__(self, bits_sign=(bits, 1), *args, **kwargs)
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# Reduction ----------------------------------------------------------------------------------------
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from functools import reduce
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from operator import and_, or_, not_, xor, add
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def Reduce(operator, value):
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# List of supported Operators.
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operators = {
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"AND" : and_,
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"OR" : or_,
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"NOR" : not_,
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"XOR" : xor,
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"ADD" : add,
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}
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# Switch to upper-case.
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operator = operator.upper()
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# Check if provided operator is supported.
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if operator not in operators.keys():
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supported = ", ".join(operators.keys())
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raise ValueError(f"Reduce does not support {operator} operator; supported: {supported}.")
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# Return Python's reduction.
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return reduce(operators[operator], value)
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@ -0,0 +1,17 @@
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#
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# This file is part of LiteX.
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#
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# This file is Copyright (c) 2023 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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# LiteX Context ------------------------------------------------------------------------------------
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# FIXME: PoC to fix Efinix AsyncFIFO issue, think a bit more about it to see how to do it properly.
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class LiteXContext:
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platform = None
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toolchain = None
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device = None
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soc = None
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@ -0,0 +1,33 @@
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#
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# This file is part of LiteX.
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#
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# This file is Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from functools import reduce
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from operator import and_, or_, not_, xor, add
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# Reduction ----------------------------------------------------------------------------------------
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def Reduce(operator, value):
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# List of supported Operators.
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operators = {
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"AND" : and_,
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"OR" : or_,
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"NOR" : not_,
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"XOR" : xor,
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"ADD" : add,
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}
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# Switch to upper-case.
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operator = operator.upper()
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# Check if provided operator is supported.
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if operator not in operators.keys():
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supported = ", ".join(operators.keys())
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raise ValueError(f"Reduce does not support {operator} operator; supported: {supported}.")
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# Return Python's reduction.
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return reduce(operators[operator], value)
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@ -0,0 +1,21 @@
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#
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# This file is part of LiteX.
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#
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# This file is Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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# Signals ------------------------------------------------------------------------------------------
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class Open(Signal): pass
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class Unsigned(Signal):
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def __init__(self, bits=1, *args, **kwargs):
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assert isinstance(bits, int)
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Signal.__init__(self, bits_sign=(bits, 0), *args, **kwargs)
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class Signed(Signal):
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def __init__(self, bits=1, *args, **kwargs):
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assert isinstance(bits, int)
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Signal.__init__(self, bits_sign=(bits, 1), *args, **kwargs)
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