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sdram/module: add MT47H128M8 DDR2 (used for a customer)

This commit is contained in:
Florent Kermarrec 2015-03-21 18:52:10 +01:00
parent 45eb5090db
commit 0f9b0c6f0f
1 changed files with 17 additions and 0 deletions
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17
misoclib/mem/sdram/module.py
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@ -138,6 +138,23 @@ class MT46H32M16(SDRAMModule):
self.timing_settings)
# DDR2
class MT47H128M8(SDRAMModule):
geom_settings = {
"nbanks": 8,
"nrows": 16384,
"ncols": 1024
}
timing_settings = {
"tRP": 15,
"tRCD": 15,
"tWR": 15,
"tWTR": 2,
"tREFI": 7800,
"tRFC": 127.5
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings,
self.timing_settings)
# DDR3
class MT8JTF12864(SDRAMModule):