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soc/integration/soc: add_etherbone/ClockDomainRenamer: keep sys connected to sys instead of eth rx

This commit is contained in:
Gwenhael Goavec-Merou 2024-02-07 07:20:31 +01:00
parent 57bc0369c7
commit 13c57e8304
1 changed files with 1 additions and 2 deletions
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3
litex/soc/integration/soc.py
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@ -1834,8 +1834,7 @@ class LiteXSoC(SoC):
# Use PHY's eth_tx/eth_rx clock domains.
ethcore = ClockDomainsRenamer({
"eth_tx": phy_cd + "_tx",
"eth_rx": phy_cd + "_rx",
"sys": phy_cd + "_rx"})(ethcore)
"eth_rx": phy_cd + "_rx"})(ethcore)
self.add_module(name=f"ethcore_{name}", module=ethcore)
etherbone_cd = "sys"