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integration/soc/add_ethernet: Use separates TX/RX buses/regions for ethmac. 

LiteEth corresponding PR: https://github.com/enjoy-digital/liteeth/pull/161.
This commit is contained in:
Florent Kermarrec 2024-06-25 17:39:26 +02:00
parent 1ad0f828bb
commit 14a640302c
2 changed files with 47 additions and 6 deletions
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27
litex/soc/integration/soc.py
View File

@ -1871,10 +1871,31 @@ class LiteXSoC(SoC):
"eth_tx": phy_cd + "_tx", "eth_tx": phy_cd + "_tx",
"eth_rx": phy_cd + "_rx"})(ethmac) "eth_rx": phy_cd + "_rx"})(ethmac)
self.add_module(name=name, module=ethmac) self.add_module(name=name, module=ethmac)
# Compute Regions size and add it to the SoC. # Compute Regions size and add it to the SoC.
ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant ethmac_rx_region_size = ethmac.rx_slots.constant*ethmac.slot_size.constant
ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=ethmac_region_size, cached=False) ethmac_tx_region_size = ethmac.tx_slots.constant*ethmac.slot_size.constant
self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region) ethmac_region_size = ethmac_rx_region_size + ethmac_tx_region_size
self.bus.add_region(name, SoCRegion(
origin = self.mem_map.get(name, None),
size = ethmac_region_size,
linker = True,
cached = False,
))
ethmac_rx_region = SoCRegion(
origin = self.bus.regions[name].origin + 0,
size = ethmac_rx_region_size,
linker = True,
cached = False,
)
self.bus.add_slave(name=f"{name}_rx", slave=ethmac.bus_rx, region=ethmac_rx_region)
ethmac_tx_region = SoCRegion(
origin = self.bus.regions[name].origin + ethmac_rx_region_size,
size = ethmac_tx_region_size,
linker = True,
cached = False,
)
self.bus.add_slave(name=f"{name}_tx", slave=ethmac.bus_tx, region=ethmac_tx_region)
# Add IRQs (if enabled). # Add IRQs (if enabled).
if self.irq.enabled: if self.irq.enabled:

26
litex/tools/litex_sim.py
View File

@ -262,9 +262,29 @@ class SimSoC(SoCCore):
interface = "wishbone", interface = "wishbone",
endianness = self.cpu.endianness endianness = self.cpu.endianness
) )
ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant ethmac_rx_region_size = ethmac.rx_slots.constant*ethmac.slot_size.constant
ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False) ethmac_tx_region_size = ethmac.tx_slots.constant*ethmac.slot_size.constant
self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region) ethmac_region_size = ethmac_rx_region_size + ethmac_tx_region_size
self.bus.add_region("ethmac", SoCRegion(
origin = self.mem_map.get("ethmac", None),
size = ethmac_region_size,
linker = True,
cached = False,
))
ethmac_rx_region = SoCRegion(
origin = self.bus.regions["ethmac"].origin + 0,
size = ethmac_rx_region_size,
linker = True,
cached = False,
)
self.bus.add_slave(name="ethmac_rx", slave=ethmac.bus_rx, region=ethmac_rx_region)
ethmac_tx_region = SoCRegion(
origin = self.bus.regions["ethmac"].origin + ethmac_rx_region_size,
size = ethmac_tx_region_size,
linker = True,
cached = False,
)
self.bus.add_slave(name="ethmac_tx", slave=ethmac.bus_tx, region=ethmac_tx_region)
# Add IRQs (if enabled). # Add IRQs (if enabled).
if self.irq.enabled: if self.irq.enabled: