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cores/gpio/GPIOTristate: Use Record.flatten() instead of Record.raw_bits().

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Fix verilog syntax error.
This commit is contained in:
Florent Kermarrec 2021-11-30 15:48:34 +01:00
parent 9036050364
commit 16a43e983e
1 changed files with 1 additions and 1 deletions
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2
litex/soc/cores/gpio.py
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@ -85,7 +85,7 @@ class GPIOTristate(_GPIOIRQ, Module, AutoCSR):
# Internal Tristate. # Internal Tristate.
if internal: if internal:
if isinstance(pads, Record): if isinstance(pads, Record):
pads = pads.raw_bits() pads = pads.flatten()
# Proper inout IOs. # Proper inout IOs.
for i in range(nbits): for i in range(nbits):
t = TSTriple() t = TSTriple()