cores/gpio/GPIOTristate: Use Record.flatten() instead of Record.raw_bits().
Fix verilog syntax error.
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@ -85,7 +85,7 @@ class GPIOTristate(_GPIOIRQ, Module, AutoCSR):
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# Internal Tristate.
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if internal:
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if isinstance(pads, Record):
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pads = pads.raw_bits()
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pads = pads.flatten()
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# Proper inout IOs.
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for i in range(nbits):
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t = TSTriple()
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