compat/soc_core: Fix register_mem/rom missing imports.
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@ -67,10 +67,12 @@ class SoCCoreCompat:
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def register_mem(self, name, address, interface, size=0x10000000):
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compat_notice("SoCCore.register_mem", date="2022-11-03", info="Switch to SoC.bus.add_slave(...)")
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from litex.soc.integration.soc import SoCRegion
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self.bus.add_slave(name, interface, SoCRegion(origin=address, size=size))
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def register_rom(self, interface, rom_size=0xa000):
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compat_notice("SoCCore.register_mem", date="2022-11-03", info="Switch to SoC.bus.add_slave(...)")
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from litex.soc.integration.soc import SoCRegion
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self.bus.add_slave("rom", interface, SoCRegion(origin=self.cpu.reset_address, size=rom_size))
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# Finalization ---------------------------------------------------------------------------------
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