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litex_sim: Find tapcfg from pythondata module.

This commit is contained in:
Tim 'mithro' Ansell 2020-04-11 18:34:29 -07:00
parent 3aee8a5227
commit 1f35669508
4 changed files with 10 additions and 9 deletions
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6
litex/build/sim/core/modules/ethernet/Makefile
View File

@ -3,7 +3,7 @@ UNAME_S := $(shell uname -s)
include $(SRC_DIR)/modules/rules.mak include $(SRC_DIR)/modules/rules.mak
CFLAGS += -I$(MOD_SRC_DIR)/tapcfg/src/include CFLAGS += -I$(TAPCFG_DIRECTORY)/src/include
OBJS = $(MOD).o tapcfg.o taplog.o OBJS = $(MOD).o tapcfg.o taplog.o
$(MOD).so: $(OBJS) $(MOD).so: $(OBJS)
@ -13,8 +13,8 @@ else
$(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $^ $(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $^
endif endif
tapcfg.o: $(MOD_SRC_DIR)/tapcfg/src/lib/tapcfg.c tapcfg.o: $(TAPCFG_DIRECTORY)/src/lib/tapcfg.c
$(CC) $(CFLAGS) -c -o $@ $< $(CC) $(CFLAGS) -c -o $@ $<
taplog.o: $(MOD_SRC_DIR)/tapcfg/src/lib/taplog.c taplog.o: $(TAPCFG_DIRECTORY)/src/lib/taplog.c
$(CC) $(CFLAGS) -c -o $@ $< $(CC) $(CFLAGS) -c -o $@ $<

6
litex/build/sim/core/modules/xgmii_ethernet/Makefile
View File

@ -3,7 +3,7 @@ UNAME_S := $(shell uname -s)
include $(SRC_DIR)/modules/rules.mak include $(SRC_DIR)/modules/rules.mak
CFLAGS += -I$(MOD_SRC_DIR)/tapcfg/src/include CFLAGS += -I$(TAPCFG_DIRECTORY)/src/include
OBJS = $(MOD).o tapcfg.o taplog.o OBJS = $(MOD).o tapcfg.o taplog.o
$(MOD).so: $(OBJS) $(MOD).so: $(OBJS)
@ -13,8 +13,8 @@ else
$(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $^ $(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $^
endif endif
tapcfg.o: $(MOD_SRC_DIR)/tapcfg/src/lib/tapcfg.c tapcfg.o: $(TAPCFG_DIRECTORY)/src/lib/tapcfg.c
$(CC) $(CFLAGS) -c -o $@ $< $(CC) $(CFLAGS) -c -o $@ $<
taplog.o: $(MOD_SRC_DIR)/tapcfg/src/lib/taplog.c taplog.o: $(TAPCFG_DIRECTORY)/src/lib/taplog.c
$(CC) $(CFLAGS) -c -o $@ $< $(CC) $(CFLAGS) -c -o $@ $<

1
litex/build/sim/core/modules/xgmii_ethernet/tapcfg
View File

@ -1 +0,0 @@
../ethernet/tapcfg/

6
litex/build/sim/verilator.py
View File

@ -7,7 +7,7 @@ import sys
import subprocess import subprocess
from migen.fhdl.structure import _Fragment from migen.fhdl.structure import _Fragment
from litex import get_data_mod
from litex.build import tools from litex.build import tools
from litex.build.generic_platform import * from litex.build.generic_platform import *
@ -102,13 +102,15 @@ extern "C" void litex_sim_init(void **out)
def _generate_sim_variables(include_paths): def _generate_sim_variables(include_paths):
tapcfg_dir = get_data_mod("misc", "tapcfg").data_location
include = "" include = ""
for path in include_paths: for path in include_paths:
include += "-I"+path+" " include += "-I"+path+" "
content = """\ content = """\
SRC_DIR = {} SRC_DIR = {}
INC_DIR = {} INC_DIR = {}
""".format(core_directory, include) TAPCFG_DIRECTORY = {}
""".format(core_directory, include, tapcfg_dir)
tools.write_to_file("variables.mak", content) tools.write_to_file("variables.mak", content)