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Merge pull request #2102 from Dolu1990/vexiiriscv-macsg
Vexiiriscv update
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commit
23df960859
1 changed files with 31 additions and 1 deletions
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@ -63,6 +63,7 @@ class VexiiRiscv(CPU):
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jtag_instruction = False
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with_cpu_clk = False
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vexii_video = []
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vexii_macsg = []
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vexii_args = ""
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@ -143,6 +144,7 @@ class VexiiRiscv(CPU):
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cpu_group.add_argument("--l2-self-flush", default=None, help="VexiiRiscv L2 ways will self flush on from,to,cycles")
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cpu_group.add_argument("--with-axi3", action="store_true", help="mbus will be axi3 instead of axi4")
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cpu_group.add_argument("--vexii-video", action="append", default=[], help="Add the memory coherent video controller")
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cpu_group.add_argument("--vexii-macsg", action="append", default=[], help="Add the memory coherent ethernet mac")
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@ -154,7 +156,7 @@ class VexiiRiscv(CPU):
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vdir = get_data_mod("cpu", "vexiiriscv").data_location
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ndir = os.path.join(vdir, "ext", "VexiiRiscv")
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NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "e7c9f4a3", args.update_repo)
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NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "ca10ab58", args.update_repo)
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if not args.cpu_variant:
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args.cpu_variant = "standard"
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@ -209,6 +211,7 @@ class VexiiRiscv(CPU):
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if args.l2_self_flush:
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VexiiRiscv.l2_self_flush = args.l2_self_flush
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VexiiRiscv.vexii_video = args.vexii_video
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VexiiRiscv.vexii_macsg = args.vexii_macsg
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def __init__(self, platform, variant):
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@ -232,6 +235,8 @@ class VexiiRiscv(CPU):
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i_litex_clk = ClockSignal("sys"),
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i_litex_reset = ResetSignal("sys") | self.reset,
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o_debug=self.tracer_payload,
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# Patcher/Tracer.
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# o_patcher_tracer_valid = self.tracer_valid,
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# o_patcher_tracer_payload = self.tracer_payload,
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@ -343,6 +348,28 @@ class VexiiRiscv(CPU):
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self.cpu_params["o_" + name + "_colorEn"] = color_en
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self.cpu_params["o_" + name + "_color"] = color
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def add_io(direction, prefix, name, width):
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composed = prefix + "_" + name
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sig = Signal(width, name = composed)
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setattr(self, composed, sig)
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self.cpu_params[direction + "_" + composed] = sig
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for macsg in VexiiRiscv.vexii_macsg:
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args = {}
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for i, val in enumerate(macsg.split(",")):
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name, value = val.split("=")
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args.update({name: value})
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name = args["name"]
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add_io("i", name, "tx_ref_clk", 1)
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add_io("o", name, "tx_ctl", 2)
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add_io("o", name, "tx_d", 8)
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add_io("o", name, "tx_clk", 2)
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add_io("i", name, "rx_ctl", 2)
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add_io("i", name, "rx_d", 8)
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add_io("i", name, "rx_clk", 1)
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@ -369,6 +396,7 @@ class VexiiRiscv(CPU):
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md5_hash.update(str(VexiiRiscv.memory_regions).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.vexii_args).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.vexii_video).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.vexii_macsg).encode('utf-8'))
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md5_hash.update(str(VexiiRiscv.with_opensbi).encode('utf-8'))
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# md5_hash.update(str(VexiiRiscv.internal_bus_width).encode('utf-8'))
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@ -409,6 +437,8 @@ class VexiiRiscv(CPU):
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gen_args.append(f"--with-axi3")
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for arg in VexiiRiscv.vexii_video:
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gen_args.append(f"--video {arg}")
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for arg in VexiiRiscv.vexii_macsg:
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gen_args.append(f"--mac-sg {arg}")
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cmd = f"""cd {ndir} && sbt "runMain vexiiriscv.soc.litex.SocGen {" ".join(gen_args)}\""""
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