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integration/soc/add_video_terminal: Connect UART to TX FIFO instead of Source. 

Allow UART to be displayed on terminal with Auto TX flush.
This commit is contained in:
Florent Kermarrec 2021-05-28 11:11:19 +02:00
parent ad1fe143cc
commit 26db10701a
1 changed files with 2 additions and 2 deletions
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4
litex/soc/integration/soc.py
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@ -1732,8 +1732,8 @@ class LiteXSoC(SoC):
uart_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from="sys", cd_to=clock_domain) uart_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from="sys", cd_to=clock_domain)
setattr(self.submodules, f"{name}_uart_cdc", uart_cdc) setattr(self.submodules, f"{name}_uart_cdc", uart_cdc)
self.comb += [ self.comb += [
uart_cdc.sink.valid.eq(self.uart.source.valid & self.uart.source.ready), uart_cdc.sink.valid.eq(self.uart.tx_fifo.source.valid & self.uart.tx_fifo.source.ready),
uart_cdc.sink.data.eq(self.uart.source.data), uart_cdc.sink.data.eq(self.uart.tx_fifo.source.data),
uart_cdc.source.connect(vt.uart_sink), uart_cdc.source.connect(vt.uart_sink),
] ]