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sdram working on PPro

This commit is contained in:
Sebastien Bourdeauducq 2015-09-26 21:51:22 +08:00
parent 67133f3542
commit 27b2383607
4 changed files with 11 additions and 9 deletions
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4
misoc/cores/dfii.py
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@ -1,7 +1,7 @@
from migen import *
from migen.bank.description import *
from misoc.mem.sdram.phy import dfi
from misoc.interconnect import dfi
from misoc.interconnect.csr import *
class PhaseInjector(Module, AutoCSR):

1
misoc/cores/lasmicon/__init__.py
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@ -0,0 +1 @@
from misoc.cores.lasmicon.core import LASMIcon

1
misoc/cores/sdram_phy/gensdrphy.py
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@ -23,6 +23,7 @@
from migen import *
from migen.genlib.record import *
from migen.fhdl.specials import Tristate
from misoc.interconnect.dfi import *
from misoc.cores import sdram_settings

14
misoc/integration/soc_sdram.py
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@ -1,9 +1,9 @@
from migen import *
from migen.genlib.record import *
from misoc.interconnect import wishbone, wishbone2lasmi
from misoc.interconnect import wishbone, wishbone2lasmi, lasmi_bus
from misoc.interconnect.csr import AutoCSR
from misoc.cores import sdram_tester
from misoc.cores import sdram_tester, dfii, minicon, lasmicon
from misoc.integration.soc_core import SoCCore
# TODO: cleanup
@ -19,7 +19,7 @@ class SDRAMCore(Module, AutoCSR):
self.comb += Record.connect(self.dfii.master, phy.dfi)
# LASMICON
if isinstance(controller_settings, lasmicon.LASMIconSettings):
if isinstance(controller_settings, LASMIconSettings):
self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings,
geom_settings,
timing_settings,
@ -27,11 +27,11 @@ class SDRAMCore(Module, AutoCSR):
**kwargs)
self.comb += Record.connect(controller.dfi, self.dfii.slave)
self.submodules.crossbar = lasmixbar.LASMIxbar([controller.lasmic],
self.submodules.crossbar = lasmi_bus.LASMIxbar([controller.lasmic],
controller.nrowbits)
# MINICON
elif isinstance(controller_settings, minicon.MiniconSettings):
elif isinstance(controller_settings, MiniconSettings):
self.submodules.controller = controller = minicon.Minicon(phy.settings,
geom_settings,
timing_settings)
@ -107,7 +107,7 @@ class SoCSDRAM(SoCCore):
# XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
# Remove this workaround when fixed by Xilinx.
from mibuild.xilinx.vivado import XilinxVivadoToolchain
from migen.build.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
from migen.fhdl.simplify import FullMemoryWE
self.submodules.l2_cache = FullMemoryWE()(l2_cache)
@ -122,7 +122,7 @@ class SoCSDRAM(SoCCore):
# XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
# Remove this workaround when fixed by Xilinx.
from mibuild.xilinx.vivado import XilinxVivadoToolchain
from migen.build.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
from migen.fhdl.simplify import FullMemoryWE
self.submodules.l2_cache = FullMemoryWE()(l2_cache)