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vexii non coherent config write bandwidth improvment

This commit is contained in:
Dolu1990 2024-06-13 23:20:25 +02:00
parent 2e4813d6ae
commit 28d4aff10f
1 changed files with 1 additions and 1 deletions
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2
litex/soc/cores/cpu/vexiiriscv/core.py
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@ -148,7 +148,7 @@ class VexiiRiscv(CPU):
vdir = get_data_mod("cpu", "vexiiriscv").data_location vdir = get_data_mod("cpu", "vexiiriscv").data_location
ndir = os.path.join(vdir, "ext", "VexiiRiscv") ndir = os.path.join(vdir, "ext", "VexiiRiscv")
NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "66974d1e", args.update_repo) NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "e991b315", args.update_repo)
if not args.cpu_variant: if not args.cpu_variant:
args.cpu_variant = "standard" args.cpu_variant = "standard"